CMOS-Compatible Logic Embedded High-K Charge-Trap Multi...

CMOS-Compatible Logic Embedded High-K Charge-Trap Multi-Time-Programmable Memory

Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer

Outline

•  Introduction •  Embedded Nonvolatile Memory Applications •  Charge Trap Transistor (CTT) Technology •  Macro Overview •  Hardware Results •  SOI •  14nm Bulk FinFET

•  Future scope •  Summary

2

Introduction – Computer Architecture

3

CPU Memory DRAM

Firmware (BIOS) ROM OTPM / MTPM

Hard Disk NVRAM CDROM TAPE

Ext. Cache Memory L4: eDRAM

Input / Output Controllers

Keyboard Mouse Monitor Printer

Cache Memory L1: SRAM L2: SRAM/eDRAM L3: eDRAM Chip ID : OTPM

Network

Memory

Peripherals

CPU


4

CPU Memory DRAM







Network

Memory

Peripherals

CPU


5

CPU Memory DRAM







Network

Memory

Peripherals

CPU

Integration is beneficial

Some integ. beneficial for mobile applications. Low Cost with process & test adders?? -  Why not interposer or 3D solution ?

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache

Emerging Memory (MRAM)

Improve Performance Reduce Power

Improve Security

Small System Space

New Applications

6

L3 cache

cac

he

OTPM ID,

Redund- ancies

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache



Improve Security

Small System Space

New Applications

7

L3 cache

cac

he

OTPM ID,

Redund- ancies

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache



Improve Security

Small System Space

New Applications

8

L3 cache

cac

he

OTPM ID,

Redund- ancies

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache



Improve Security

Small System Space

New Applications

9

L3 cache

cac

he

OTPM ID,

Redund- ancies

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache



Improve Security

Small System Space

New Applications

10

L3 cache

cac

he

OTPM ID,

Redund- ancies

Embedded Memories

Embedded System

DRAM (Main Memory)

Flash (SSD/Media)

SRAM Cache



Improve Security

Small System Space

New Applications

11

L3 cache

cac

he

OTPM ID,

Redund- ancies

Outline



12

Embedded Nonvolatile Memories

•  Integrating Firmware on chip is beneficial

•  Cost reduction à If done with zero-mask adder to logic process.

•  Enhanced security. Slide 13 13

Type

Tech-nique

Density

Re-writability

OTPM eFUSE Low One Time

Dense OTPM

Anti-fuse Medium Emulation

MTPM Charge Trap

Medium Medium

Flash FG High High

MRAM Magnetic High High ID

2D R

ed.

3D R

ed.

Firm

war

e

Dat

a

Cac

he

Sec

urity

Applications

Ideally suited

Fairly suited

Somewhat suited

Not suited

eNVM For Redundancy

14

OTPM

eDRAM

P. Klim et. al, VLSI 2008

3D memory requires significantly more OTPMs

15

eNVM for Automotive application

•  4MB code flash + 64KB data flash integrated on-chip.

•  Targeted for automotive MCUs for engine control and driver assistance applications.

Y. Taito et al., ISSCC 2015

eNVM for Media application

16

Embedded Flash memory in 0.5um CMOS for voice-storage application: •  32Mb, 4-level embedded flash

to store 64 minutes of voice.

•  On-chip Memory BIST is included.

M. Borgatti et al., IEEE JSSC 2001

eNVM for other applications

17

STT-MRAM based cache memory in 65nm node, H. Noguchi et al., ISSCC 2016 Memory cell : 2T 2MTJ

Nonvolatile logic-in-memory array processor using MTJ/MOS in 90nm node, M. Natsui et al., ISSCC 2013 .

Outline



18

This talk focuses on a CTT based eNVM targeted for : •  Secure OTPM ID •  2D and 3D Redundancies •  Firmware applications

Comparison of Embedded NVRAM Solutions

Floating Gate •  Dual poly [1]

Charge Trap NVM

BEOL NVM •  ReRAM [3] •  STT MRAM[4]

OTPM •  eFuse [5] •  Anti Fuse [6]

Process Overhead High Voltage Process Overhead One Time

Programmable

n+ n+ n+ n+ n+ n+

HiK dielectric for logic

Split Gate SGMONOS [2] •  CHE in Si3N4 in Split Gate •  Voltage ~ 7-10V

OTP from NSCore [9] •  CHE in Si3N4 Side wall spacer •  Voltage ~ 5-7V

CTT [This Work] •  CHE in HiK HfO2 •  Voltage ~ 1.5-2V

Side Wall Spacer Split Gate

CTT – Dense, No mask adder, Bulk/ SOI FIN scalable, logic voltage compatible MTPM

19

CTT MTPM Applications

Density

Num

ber o

f writ

es

1MB ID Repair Code Data

Few Multi-Writes

>> 1M Rewrites Multi-Writes

CTT MTPM

Anti-Fuse (MTP Emulation)

Embedded Flash Additional process FIN: Very difficult

External Flash

OTP

1K

1KB

eFUSE

2D 3D

20

# Writes

1GB

Outline



21

Charge Trap Transistor (CTT) Technology

22

Intrinsic Oxygen vacancies in HfO2 HiK dielectrics

Charge Trapping done at logic process compatible voltages

S D SL = 1.5V BL=0V

WL= 2.0 V

Charge trapping mechanism: Intrinsic Oxygen vacancies in HfO2 [7]

Hafnium Atom Oxygen

Atom

Released Oxygen Atom

Oxygen Vacancy

HiK Logic NMOS - Program S D SL = 2 V BL=Float

WL= -1 V

HiK Logic NMOS Transistor - Erase

OTPM / MTPM Twin Cell

SL BLc BLt

MTPM Twin Cell

e- + DVT

BLt BLc BL

WL WL

WL

6T SRAM 0.169mm2 in 32nm node 1T1C DRAM 0.039mm2 in 32nm node

0.108mm2 in 32nm node

23

1/4 Standby – Initial State Before Programming

Mode WL BL SL

Standby 0V float 0V

Program 2V 0V ~1.5V

Read 1V Signal 1V

Erase -1V float ~2V

WL

BLt BLc SL

24

2/4 Program

Mode WL BL SL

Standby 0V float 0V

Program 2V 0V ~1.5V

Read 1V Signal 1V

Erase -1V float ~2V

WL=2V

BLt=0V BLc

e-

SL=1.5V

25

WL=0V

3/4 Read

Mode WL BL SL

Standby 0V float 0V

Program 2V 0V ~1.5V

Read 1V Signal 1V

Erase -1V float ~2V

26

WL=1V

BLt BLc

e-

DSA = VBLt – VBLc OR IBLt - IBLc

SL=1V

4/4 Erase

Mode WL BL SL

Stand-by 0V float 0V

Program 2V 0V ~1.5V

Read 1V Signal 1V

Erase -1V float ~2V

WL=-1V

BLt BLc SL=2V

27

WL=-1V

CTT : Operating zones

28

Circuit Assist Techniques needed to operate in the “Safe” Zone

S D

SL = 1.5V BL=0V

WL= 2.0 V

100

200

300

10 1 100

Breakdown

Safe

400

Increasing WL voltage improves prog. time

Prog. Time (ms) Retention Time (Log Scale)

DV

TH (

a.u)

DVTH recovery

Increasing SL voltage improves retention

DV

TH (

a.u)

29

eFUSE Anti Fuse MTPM Mb/(mm2) <0.1 ~1 ~1 Rewritable No No Yes

1st Write 2nd Write

Bitmap Image

HiK Charge Trap Transistor Enables Process Free Multi-time Programmability

80Kb Array

BL Drivers

SA and OWP circuit

SL Switches WL Drivers

Control

Control

Outline



30

80Kb Twin Cell Macro Architecture

80Kb Array

BL Drivers

SA and OWP circuit

SL Switches WL Drivers

Control

Control

80 Data Line (DL) Read Out(80X4 = 320 Bit Lines)

256 WLs

Protection devices not shown

DIN

CSL

SA

OWP OWP

SA_DOUT

WL

BLt

BLc

S

L

1X4

VSL_EN VSL

BLc BLt

WL

SL

NMOSt Increase VTt (program)

NMOSc Keep VTc (unprogram)

BLt BLc

SL

SL

SL

SL Bit-Cell Layout

Detect DIFVT DIFVT = VTt -VTc

32

Overwrite: Too much VT Shift (TDDB Risk)

DIF

VT

Dis

tribu

tion

(Nor

mal

ized

)

Before Programming

After Programming

Overwrite Protection

Overwrite Protection

Insufficient write Too small VT Shift (Retention Risk)

BLc BLt

WL SL

NMOSt VTt (program)

NMOSc VTc (unprogrammed)

DIFVT = VTt - Vtc

Circuit Assist – Over Write Protection

MASK

Program Cycle 1

Read Cycle 1

Program Cycle 2

Read Cycle 2

Margin Write

Cell a DIN=1

DOUT=1 Matches

DIN

DOUT= 1 Match

Cell b

DIN = 1

DOUT=0 Mismatch with DIN

DOUT=1 Match

T C VTt VTc VTt VTc VTt VTc

Comparable VTH difference = (VTt – Vtc)

Cell a

Cell b

Cell x

Cycle

Write Verify

OWP

OWP

OWP

Margin Write/Verify

Write in multi-steps with OWP

33

Circuit Assist – Block Write

Step 1: Initial write (w) Step 2&3: read+verify+write (rvw) (rewrite if not verified correctly)

Step 4: margin write (mw)

OWP

Cycle v v p p p p v v p p v v p p v v p p v v p p

Cell 0,a v p p v v v p

Cell 0,b v p p v p v p v p p

v p p v p v p v p Cell 1,a

v p p v p v v p Cell 1,b

OWP

OWP

Step1 Step2 -3 Step4

Column

Cell a plane Cell b plane

ROW

0w 4w

5w

2w

3w 7w

9w

NA

NA

NA

NA

NA

10w

1w

6w

8w 0rvw 4rvw

5rvw

2rvw

3rvw

9rvw

10rvw 6rvw

8rvw

1rvw

7rvw

SAOUT W Data =

0mw 4mw

5mw

2mw

3mw

9mw

10mw

1mw

7mw

8mw

Initial

In progress

Insufficient prog. (need rewrite)

1 prog. cell

0 prog. cell

program verify

6mw

Slide 11

Circuit Assist – Slew Sense Amplifier

NMOSt NMOSc

WL

SL

Cell B

Lt

BLc

SA

t

SA

c

PREDISCH

VDD

I0 I1 P0 P1

SA_DOUT

SSA

CSL(1/4) CSL (1/4)

  Turn on column switch

  Connect cell to SA

  Ramp the WL slowly to VDD

  Rise time ~500ps

  Differential charging of SAt and SAc

  Self timed Sense Amp

  Capacitance mismatch

  Fixable using reduced slew


NMOSt NMOSc

WL

SL

Cell B

Lt

BLc

SA

t

SA

c

PREDISCH

VDD

I0 I1 P0 P1

SA_DOUT

SSA

CSL(1/4) CSL (1/4)

NMOSc is still OFF

NMOSt turns ON in Saturation

WL (~500ps Rise)

PREDISCH

SAt

SAc

SA_DOUT


NMOSt NMOSc

WL

SL

BLt

BLc

SSA

CBLT CBLC VDD VDD

CSL CSL SET

SAt SAc

Load

0.01

0.1

1

10

100

1000

10000

100 120 140 160 180 200

Fails

/mill

ion

VTH Differential ( mV )

SSA

CCSA

CCSA

SSA can sense 10% less VT shift compared to CCSA

Outline



38

SOI Hardware Results - OWP

39

a: Without OWP b: With OWP

Time(ms) Time(ms)

OW Fails

Per

fect

Per

fect

Per

fect

Per

fect

Per

fect

Over-Write Protection ensures operation in the “safe” zone

32nm SOI

Needs More Programming

J. Viraraghavan et al., IEEE VLSI Symp. 2016

SOI Hardware Results – HTS Stress

40

Bake Tests Indicate 30% VTH Degradation in 10 years @ 125OC

32nm SOI

SOI Hardware Results – Multi-Time Programming

41

1 Data 0 Data

a: Multiple Write (4X) with OWP Inverted

PRE – Initial State W – Write/ Program ER - Erase

J. Viraraghavan et al., IEEE VLSI Symp. 2016

Outline

•  Introduction •  Embedded Nonvolatile Memory Applications •  Charge Trap Transistor (CTT) Technology •  Macro Overview •  Hardware Results •  SOI •  14nm bulk FinFET


42

43

1st Write 4th Write

3rd Write

2nd Write

Pre

14nm bulk FinFET Hardware Results 40Kb Checker Board Programming

256b Multi Programming

44

Prototype is functional using VDD = 0.7V

Projected Charge loss for 10 year product life: <35%

Cycle Time (ns)

VD

D (V

)

14nm Hardware Results - Schmoo and retention

Outline



45

Future : Endurance Improvement Concept

46

S

SL BL G

D S

SL BL

Higher gate voltage & long time to create

more vacancies

D

Process Phase Manufacturing Test Phase

SL BL

Low gate voltage & short time to avoid

new vacancies

User Phase

Initially few vacancies

G G

S D Trapping &

detrapping

Future : Hardware-Based Security

47

§ Programmed bits physically invisible

§ Enable Physically Unclonable Fuse (PUF) for a secure product source solution.

§ Create a unified memory array, using these three modes of operation

– OTPM Mode: Used for stable non-volatile bits

– MTPM Mode: Self Destructive Re-writable Memory non-volatile bits

– Intrinsic ID Mode: Physically Unclonable Fuse (PUF).

BLc BLt

e- WL

SL

NMOSt NMOSc

Twi Cell Memory Cell

Future : Unified memory using CTT MTPM

48

SL

Sense Amps

Bitline Drivers

Error Correction Code Logic

OTPM / MTPM / PUF

Random VT

ECC w/ OTPM bits ECC

Self-Destructive Re-write

OTPM

MTPM

PUF

Rewritable

Outline



49

Summary

50

•  MTPM demonstrated in both SOI and Bulk FIN •  Scalable standard Hi-K logic process

•  Process as it is (ex. No mask adder) •  Operated in logic compatible voltages •  ~30X more dense than eFUSE

•  Future : MTPM fundamental concepts •  Endurance improvement, using forming approach •  Unified memory, using OTPM, self-destructive MTPM, PUF.

Technology 32nm SOI 22nm SOI 14nm FIN Bulk

Cell 0.109µm2 with 1.4nm Gox NMOS

0.144µm2 with 1.2nm Gox NMOS

0.1411µm2 with FIN NMOS

Macro Density 80Kb 64Kb 40Kb

Density/mm2 ~2Mb/mm2 ~2.5Mb/mm2 ~1.3*Mb/mm2

Activation Energy ~1.4eV - ~1.6eV

References

51

[1] H. Kojima et. al., IEDM, 2007, pp. 677–680. [2] Y. Taito et. al., ISSCC, pp. 132-133, Feb. 2015. [3] M. Jefremow et. al., ISSCC, pp. 216-217, Feb. 2013. [4] M. Ueki et. al, VLSI Tech., pp. 108-109, 2015. [5] G. Uhlmann et. al., ISSCC, pp. 406-407, Feb. 2008. [6] Zicheng Liu et. al., ISNE pp. 1-3, 2015 [7] C. Kothandaraman et. al., IRPS, 2015 pp. MY2.1-MY2.4 [8] F. Khan et. al., IEEE EDL 37 pp. 88-91, Jan. 2016. [9] Kenji Noda, Using Hot Carrier Injection for Embedded Non-volatile Memory NSCore, Inc. White Paper http://www.nscore.com/images/WhitePaper_081002.pdf

Acknowledgements

52

This work at UCLA is partially supported by the Defense Advanced Research ProjectsAgency (DARPA). The views, opinions, and/or findings contained in this article are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government

Darren Anand John Fifield Sami Rosenblatt Xiang Chen Krishnan Rengarajan Giuseppe Larosa Norman Robson Jim Pape Daniel Berger Dan Moy Robert Katz Yoann Mamy Randriamihaja Zakariae Chbili Andreas Kerber Raman Kodhandaraman

Thank You

53

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