Compact Mo delling - NXP Semiconductors · 2016. 2. 22. · bet w een foundries and design houses...
Transcript of Compact Mo delling - NXP Semiconductors · 2016. 2. 22. · bet w een foundries and design houses...
Compact Modelling
of
Submicron CMOS
D.B.M. Klaassen
Philips Research Laboratories
Eindhoven, The Netherlands
c Philips Electronics N.V. 1997
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contents
� accuracy and benchmark criteria
� new applications
{ RF modelling
� advanced process technologies
{ new physical phenomena
{ process control and parameter statistics
� conclusions
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accuracy and benchmark criteria
� compact models (and their parameters)
{ vital link in the circuit simulation chain
{ interface between
� technology engineers and circuit designers
� foundries and design houses
� need for standardization
) continuing series of SEMATECH Compact Model Workshops
� qualitative & quantitative benchmark tests for compact models
) accuracy evaluation of public-domain analog compact MOS models
{ BSIM3v3 from UC Berkeley (September 1995)
{ MOS MODEL 9 from Philips (December 1993 in public domain)
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accuracy and benchmark criteria
� mean deviation (%)
1N
NXi = 1
����Imeas � I sim
Imeas
����
� linear region
� subthreshold region
� saturation region
� output conductance
� substrate current
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accuracy and benchmark criteria0.35
gate length [micron]0.8 0.5
mean deviation [%]
3
30
10
1
subthreshold
saturation
linear
30
10
outputconductance
MOS MODEL 9
BSIM3
mean deviation (%)
1N
NXi = 1
����Imeas � I sim
Imeas
����
averaged over
whole geometry range
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new applications
) present-day compact models: accurate I-V modelling
for process technologies down to 0.35 �m
� challenges from new applications ?
DP bipolar1 µm NPN
CMOS0.5 µm N-channel
MOS MODEL 9
MEXTRAM
CMOS m N-channel0.25µ
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new applications
� RF circuit design in mainstream CMOS IC-process
� foundries supply compact model parameters for IC-processes
� public-domain analog compact MOS models
� literature on high-frequency veri�cation of compact MOS models
{ MOS MODEL 9 � Vanoppen et al., IEDM'94
� Klaassen et al., AACD'96
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new applications
ground
bulk
source
gate drain
ground
ground ground
200 um
200 um
signaal 1 signaal 2
RF measurements
� two-port S-parameter measurements
� HP8510B network analyzer
� on wafer
� air coplanar high-frequency probes
in ground-signal-ground con�guration
� special MOS structures
in common source-bulk con�guration
� S- to Y-parameter conversion
� de-embedding procedure for parasitics
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new applications: RF simulations
extrinsic elements: resistances: Rgate
; Rbulk
capacitances: gd0 ; Cgs0C
jun,d ; Cjun,sCjunction :
overlap :
Drain
Port 1
Port 2
Source Bulk
jun,dC
jun,sC
gateR
bulkR
gsoC
gdoC
intrinsic device: MOS model 9 DC-parameters oxide capacitance: +
Gate
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new applications
+V
Iin
Iout
in
� common SB con�guration
� input impedance Zin =
v ini in
� Zin � 1
j ! C e�gg
+ Rg
� N-ch. 40/1 and 100/1
� 1 �m CMOS (Vdd = 5V )
� Vds = 5:0 V ; Vgs = 2:0 V
� 5 \distributed" parallel segments
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new applications
+V
Iin
Iout
in
� common SB con�guration
� transconductance
iout
v in
�
gm � !2RgCe�dgC e�gg � j!
�gmRgCe�gg + C e�dg
�
1+
�!RgCe�gg
�2
� N-ch. 40/1; 1 �m CMOS (Vdd = 5V )
� Vds = 4:0 V ; Vgs = 4:0 V
� Rg = 0, W3L�2;poly and WL
�2;poly
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new applications
( maximum available power gain G max
� N-ch. 40/2; 1�m CMOS (Vdd = 5V )
� Vds = 5:0 V ; Vgs = 2:0 V
� N-ch. 20/0.5; 0.5�m CMOS (Vdd = 3:3V )
� Vds = 3:5 V ; Vgs = 3:5 V
� symbols: measurements
� lines: simulations
|{ with bulk resistance
- - - without bulk resistance
( phase output conductance
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new applications
RF applications
� requirements for compact models
{ accurate charge model
{ junction and overlap capacitances
{ gate and bulk resistance
) MOS MODEL 9 gives an accurate description of HF behaviour
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advanced process technologies
� present-day compact models accurate
for process technologies down to 0.35 �m
� possible requirements for future process technologies
{ incorporation of new physical phenomena
� velocity overshoot
� non-local carrier heating
� gate tunnelling
� ..............
{ process control and parameter statistics
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new physical phenomena
0.35gate length [micron]
0.8 0.5
mean deviation [%]
3
30
10
1
subthreshold
saturation
linear
30
10
outputconductance
MOS MODEL 9
BSIM3
0.25
A.H. Montree et al., ESSDERC'96:
� optimized I-line photolithography
� dry etching of BARC
� 5.5 nm gate-oxide
� advanced LOCOS �eld isolation
� twin retrograde well
� shallow junction extensions
� double avoured poly
� TiSi2 salicidation
� 0.25�m process
� 18 geometries
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new physical phenomena
Pockets (optional)
TiSi2
Source Drain
Gate
spacersTEOS
P-type wafer
TiSi2
Pockets (optional)
TiSi2
Source Drain
Gate
spacersTEOS
P-type wafer
TiSi2
J. Schmitz et al., ESSDERC'96:
� 350 nm LOCOS
� 4 nm gate-oxide
� 200 nm polysilicon + 40 nm TEOS
� E-beam patterning,HCl/HBr poly etch
� shallow drain extension implant
� spacer formation, S/D implant
� silicidation
) Lpoly = 0:18 �m
) Le� = 0:13 �m
) Vsupply = 1:8 V
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new physical phenomena: N-channel Le� = 0:13 �m
linear region saturation region
symbols: measurements
lines: MOS MODEL 9
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new physical phenomena: N-channel Le� = 0:13 �m
subthreshold region output conductance
symbols: measurements
lines: MOS MODEL 9
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new physical phenomena: N-channel Le� = 0:13 �m
avalanche generation
symbols: measurements
lines: MOS MODEL 9
� MOS MODEL 9 describes
devices down to Le� = 0:13 �m
� all physical e�ects well-modelled
) no need to take new phenomena
(e.g. velocity overshoot)
into account
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new physical phenomena
0.35gate length [micron]
0.8 0.5
mean deviation [%]
3
30
10
1
subthreshold
saturation
linear
30
10
outputconductance
MOS MODEL 9
BSIM3
0.25 0.18
) present-day compact models will be accurate
for process technologies down to 0.18 �m
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new physical phenomena
transversal electrical field
lateral electrical field
series resistance 4
3
2
11.0 0.8 0.5 0.35 0.25 0.18
design rule
reductionmobility � minimum-length devices
� saturation current
(Vgs =Vds =Vsupply)
) contributions almostconstant
� technology scaling
Ids =
�
F(Vgs ; Vds ; R series)�(Vgs � VT)Vds �
�1+ �
2
�V 2ds
�
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process control & parameter statistics
SIA roadmap ...............
0.35 0.25 0.18 0.13
gate length [micron]
1.0 0.7 0.5
supply voltage [V]
5
4
3
2
1
0
............... rapidly decreasing supply voltage
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process control & parameter statistics
0.35 0.25 0.18 0.13
gate length [micron]
supply voltage [V]
4
3
2
1
0
0.35 0.25 0.18 0.13
gate length [micron]
variation threshold voltage [mV]
80
60
40
20
0
0.35 0.25 0.18 0.13
gate length [micron]
variation threshold voltage [mV]
80
60
40
20
0
delaypower...
CIRCUIT
W/L arbitraryMM9
fingerprinting toxDvttemp...
PROCESS
DEVICE
VTOK
γ
θ
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process control & parameter statistics
process technology IC design
implantations
anneals
oxidations
..................
circuit performance
current drive
threshold voltage
subthreshold swing
EoL measurements
compact model parameters
..................
gain factor
threshold voltage
body-effect factor
..................
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process control & parameter statistics
curve �tting \direct extraction"Ids
Vgs
Vsb1(1)=0V
Vsb1(2) Vsb2(1)
Vsb2(2)
Vt0
Vgate(3)
Vgate(2)
Vgate(1)
Ids =
� (Vgs � VT)Vds
1 + �1 (Vgs � VT)
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process control & parameter statistics
W = L = 10 �m3 differentV -implantst
3 differentV -implantst
worst
best
common threshold-adjust implantation for n- and p-channels
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process control & parameter statistics
333
33
3
3-3
-3 0
0
slow
fast� W = L = 10 �m
� parameter correlations have to
be taken into account
) principal components
� devices with arbitrary geometry?
) process block
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process control & parameter statistics
M.J. van Dort et al., IEDM'95:
� 0.8 �m process
� intra-batch spread of
saturation currents of
minimum-length n- and p-channels
� 11.000 samples
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process control & parameter statistics
delaypower...
CIRCUIT
W/L arbitraryMM9
fingerprinting toxDvttemp...
PROCESS
DEVICE
VTOK
γ
θ
� distribution gate delay
� 21-stage ring oscillator
� 2000 samples
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process control & parameter statistics
source drain
W
L
Wdep
W= L = 0:25 �m
N = 2� 1017 cm�3
+
ndep � 1000;pndep � 30
+
stochastic uctuations are of the order
of several percents
� Experiments
{ Mizuno et al.,
IEEE TED 41, 2216 (1994)
{ Eisele et al.,
IEDM'95, 67 (1995)
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process control & parameter statistics
How do these intrinsic variations a�ect device performance?
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process control & parameter statisticsP.A. Stolk et al., IEDM'96:
� due to dopant uctuations
increased spread in
{ threshold voltage
{ leakage current
{ subthreshold swing
{ linear current
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process control & parameter statistics
� extract compact model parameters
� increased spread in
{ threshold voltage
{ gain factor
{ subthreshold-slope parameter
{ \transition" parameter
{ mobility reduction parameter
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process control & parameter statistics
study correlations
between parameters.....PhilipsResearch � PHILIPS
process control & parameter statistics
set of I-V curves
compact model parameters
V TOσσV TO
; β σ β ; θ1 θ1 ; .......
parameter I lin σI lin
+_+_+_
+_extraction
predictability
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advanced process technologies
� present-day compact models will be accurate
for process technologies down to 0.18 �m
� incorporation of parameter statistics in circuit simulation crucial
to obtain a realistic design window
) fast parameter extraction methods essential!
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acknowledgements
� many colleagues..............
{ Philips Research Laboratories
{ Philips Semiconductors
� JESSI/ESPRIT Project ADEQUAT+
� Technology Characterisation & Modelling Group
National Microelectronics Research Centre, Ireland
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summary & conclusions
� standardization e�orts
{ interface between foundries and design houses
{ accuracy and benchmark criteria
) present-day compact models (I-V) accurate down to 0.35 �m
� RF applications require
{ accurate charge model
{ incorporation of parasitic elements
� advanced process technologies
) present-day compact models will be accurate down to 0.18 �m
{ incorporation of parameter statistics
) evolutionary development of present-day compact models
PhilipsResearch � PHILIPS