Eca Master

8/15/2019 Eca Master

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1. COMMON EMITTER AMPLIFIER

AIM:

a)To design CE single stage amplifier with potential divider circuit using NPN

Transistor 2N2923 for the specifications : IC 3 m!" #ce $%v"β $9%" & I'$

32I( *) To o*serve dc operating point" fre+uenc, response" & C'- waveforms using

./0TI1I. software

APPARATUS: .ultisim 1oft ware

DESIGN PROCEDURE:


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CIRCUIT DIAGRAM:

PROCEDURE:-

$. 'ig up the circuit using multisim software and verif, the results using C

operating point anal,sis 4simulateanal,sis C operating point)

2 'ig up the circuit using multisim software and verif, the results using !C

anal,sis 41imulate anal,sis !C anal,sis)

3'ig up the circuit using multisim software and verif, the results usingoscilloscope


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E5PECTE 6!#E7-'.1:

RESULT:- The CE single stage amplifier is designed The C voltages andcurrents at various nodes are o*served The C transfer characteristic is plotted


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2. COMMON SOURCE AMPLIFIER

AIM: a) To design a single stage 7ET Common 1ource amplifier with potential

divider circuit using 2n8$ 7ETN channel for the following specifications:

# 28#"I $ma"#;12#"#P.!5 $3#"' 0$


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CIRCUIT DIAGRAM:

PROCEDURE:- $. 'ig up the circuit using multisim software and verif, the

results using C operating point anal,sis 4simulateanal,sis C operating

point)



3'ig up the circuit using multisim software and verif, the results using-scilloscopeExpected wave!"#$:


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RESULT: The C1 single stage amplifier is designed with the

given specifications The C operating point anal,sis is performed The fre+uenc,

response is plotted and the (and width is found


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%.T&O STAGE RC COUPLED AMPLIFIER

AIM:

=$) esign a single stage transistor amplifier with potential divider circuit 4usingan npn si transistors) with following specificationsIC$ma"#CE>v"' C22?"#CC$2v" I$$%I( and β@8 #erif, the C values

4#oltage and current) at various nodes using .ultisim software

DESIGN: IB=IC/β = 1.62/54=0.03ma

VCC=IC(RC+RE)+VCE ;

12=1.62(2.2+RE)+7.6 ;

RE=0.516k

V2=VBE+ICRE ;

V2=0.7+1.62*0.516=1.53

6v

V2=I1R2 ;

R2=V2/(I1=10IB) ;

1.536/0.3=5.12k

I1=VCC/(R1+R2) ;

(R1+R2)=12/0.3=38.1k ;

R1=38.1-5.12=32.98k

PROCEDURE: 'ig up the circuit using multisim software and verif, the

results using C operating point anal,sis 4simulate anal,sis C operating

point)

=2) esign a single stage transistor amplifier with potential divider circuit 4using

an npn si transistors) with following specifications

IC232ma"#CE@>v"' C22?"#CC$2v" I$$%I( and β33 #erif, the C

values 4#oltage and current) at various nodes using .ultisim software


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E1I;N:IB=IC/β = 2.32/33=0.07ma

VCC=IC(RC+RE)+VCE ; 12=2.32(2.2+RE)+5.7 ;

RE=0.51k

V2=VBE+ICRE ;

V2=0.7+2.32*0.51=1.88v

V2=I1R2 ; R2=V2/(I1=10IB) ;

1.88/0.7=2.68k

I1=VCC/(R1+R2) ; (R1+R2)=12/0.7=17.14k ; R1=17.14-

2.68=14.46k

PROCEDURE: 'ig up the circuit using multisim software and verif, the results usingC operating point anal,sis 4simulate anal,sis C operating point)

=3) Cascade a*ove two stages and find overall gain 4choose Cc8>∝f"

Ce8>%∝f" hfe@%) find the fre+uenc, response" C operating points and parameter sweep of load resister

ANAL'SIS:

1tage2: : AI2= -hfe/(1+hoeRL2) ; -50/(1+2/40) = -47.62

Ri2 = hie+hreAI2RL2 ;1.1+2.5e-4*-47.62*2 = 1.076k;

Av2= -AI2*RL2/Ri2 ; -47.62*2/1.076 = -.51

!"#$e-1: RL1 = 2.2k%%14.2%%2.5%%1.076 = 0.54k

AI1 = -50/(1+0.54/40) = -4&.'

Ri1 = 1.1+2.5e-4*-4&.'*0.54 = 1.106k

Av1 = -4&.'*0.54/1.106 = -24.07

ver# $#i Av = Av1*Av2 = 24.07*.51= 21'0.4

Av = Av*Ri,/(Ri,+R!) ; Ri, = 1.106%%''%%5.1= 0.k

=21'0.4*0./(0.+15) =11


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CIRCUIT DIAGRAM:


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point)



3'ig up the circuit using multisim software and verif, the results using-scilloscope

E(PECTED &A)EFORMS:


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RESULT: -*served the C voltagesAcurrents for single stage and two stageamplifiers It is o*served that Two stage amplifier gives a mid *and gain of $22%It isalso o*served that as load resistance is nearer to ' C2" the out put voltage is decreasing"since net load resistance is decreasing

*.CURRENT S+UNT FEED,AC AMPLIFIER

AIM: esign current shunt feed*ac? amplifier with a feed*ac? resistance @ -*tain C operating point and fre+uenc, response

APPARATUS: .ultisim software


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CIRCUIT DIAGRAM:



point)

2 'ig up the circuit using multisim software and verif, the results using !Canal,sis 41imulate anal,sis !C anal,sis)

3'ig up the circuit using multisim software and verif, the results using-scilloscope


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E(PECTED &A)EFORMS:

RESULT: The current shunt feed*ac? amplifier is designed with feed*ac? resistanceof @


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.&IEN ,RIDGE OSCILLATOR USING TRANSISTORS

AIM: To stud, and calculate fre+uenc, of 6ein (ridge -scillator

APPARATUS:

Transistor 4(C$%>) B 2no"

'esistors B $%


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CIRCUITDIAGRAM:

PROCEDURE:

$ Connections are made as per the circuit diagram

2 7eed the output of the oscillator to a C'- *, ma?ing adHustments in the

Potentiometer connected in the ve feed*ac? loop" tr, to o*tain a sta*le

sine 6ave

3 .easure the time period of the waveform o*tained on C'- & calculate

the 7re+uenc, of oscillations

8 'epeat the procedure for different values of capacitance

MODEL &A)E FORM:


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RESULT: wein *ridge oscillator with f T $%JK is designed The value of hfefor the designed value is computed

0.RC P+ASE S+IFT OSCILLATOR

AIM:

a) esign 'C phase shift oscillator to have resonant fre+uenc, of


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DESIGN PROCEDURE:


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CIRCUIT DIAGRAM:

VCC

12V

VCC

R1R3

100kohm4kohm

C2

10C1

Q24

2N2222A10uF

R2 11 100uF

22kohm R4

1kohm

0

C6 C5 C4

7

9R7 R6 R5


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PROCEDURE: 'ig up the circuit using multisim software and verif, the results

using -scilloscope

'E1/0T:

'C phase shift oscillator with f r


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.CLASS AA,,C PO&ER AMPLIFIERS

!I. :

To stud, the operation of Class !" Class !(" Class (" Class C poweramplifiers

!PP!'!T/1: .ultisim soft wareCI'C/IT I!;'!.:

V2 12V R2 R51kohm 1kohm

47uFC2

R3XSC1

Q147uF 30kohm G

R1 PN2369AC1T

A B

100ohm

V1R450mV

100ohm35.36mV_rms1000Hz

0D!

TJE-'M:

The classification of amplifiers is *ased on the position of the +uiescent point and etent of the characteristics that is *eing used to determine the methodof operation

There are 8 classes of operationsThe, are

$Class ! 2Class !( 3Class ( 8Class C


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C0!11 !: In class ! operation the +uiescent point and the input signal are suchthat the current in the output circuit 4at the collector) flows for all times Class !amplifier operates essentiall, over a linear portion of its characteristic there *,giving rise to minimum of distortion

C0!11 (: In class ( operation " the +uiescent point is at an etreme end of thecharacteristic " so that under +uiescent conditions the power drawn from the dc power suppl, is ver, small If the input signal is sinusoidal" amplification ta?es place for onl, half c,cle

C0!11 !(: ! class !( amplifier is the one that operates *etween the twoetremes defined for class ! and Class ( Jence the output signal eists for more

than $%% of the input signal

C0!11 C : In class C operation" the +uiescent operating point is chosen such

that output signal 4voltage or current)is Kero for more than on half of the inputsinusoidal signal c,cle

P'-CE/'E:

$ !n input sine wave 4pea?pea?)of @%m# is applied to the circuit

2 connect the output to the C'-

3 var,ing ' 3 value" o*serve and record the output waveforms for different

classes of operation

8 !lso o*serve the #i & #o waveforms using parameter sweep for different

classes of operation


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-(1E'#!TI-N1:C0!11 !:

C0!11 !( :


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XSC1

G

A BT

Rs C" 10uF #C107#P 10 uF C" 1

10 11 12 3

100ohm Q1 R$ %R

V15kohm

R5 Csh1kohm

15kohm 2&F

mV_rms 7 V'' 12V 6

z 2V

VCC

0


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P'-CE/'E:

$Connect the circuit as shown in fig and get the circuit verified *, ,ourInstructor

2 Connect the signal generator with sine wave at the input and ?eep the

amplitude to minimum position" and connect a C'- at output terminals

of the circuit

3 !ppl, the amplitude *etween $v to 88v to get the distortion less

output sine wave

8 Now" var, the input fre+uenc, in steps and o*serve and record The

output voltage

@ Calculate the gain of the tuned '7 amplifier using the formula;ain out put voltageA input voltage

plot a graph with input fre+uenc, versus gain 4in d(s)

;ain 4in d(s) 2% log 4#oA#i)

;raph :

;ain

7re+uenc,

'E1/0T:The tuned amplifier offers maimum gain at resonant fre+uenc, of the tan? circuit


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11.+ARTLE' AND COLPITT3S OSCILLATORS

AIM: To design Jartle, and ColpittOs -scillators to have resonant fre+uenc, of $)"'esistors422?F"$%%?F"$%?F"$?F)"

Capacitors4$%Qf"$%%Qf"%33 Qf)" ecade inductance *o "'P1

E4UIPMENT:

$ 1C ?it

2 7unction generator

3 C'-DESIGN PROCEDURE:

Jartle, -scillator 7 $ A 42D0e+C)6here 0e+0$02

ColpittOs -scillator 7 $ A 42D0Ce+)6here Ce+ 4c$Rc2) A 4c$c2)

CI'C/IT I!;'!.1:J!'T0EM -1CI00!T-':


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COLPITT3S OSCILLATOR:

E(PECTED &A)EFORM:

RESULT: Jartle, and ColpittOs -scillators designed for resonant fre+uenc, of $


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12. !R"I#$% !'"IIER I#$ B,%

!I':

To construct a arlington current amplifier circuit and to plot the fre+uenc, responsecharacteristics.

!!R!% REIRE:

1No Name 'ange =uantit,$ Transistor (C $%> $2 'esistor $@?F"$%?F"%F"?F $"$"$"$

3 Capacitor %$Q7" 8>Q7 2" $8 7unction ;enerator 4%3).JK $@ C'- 3%.JK $ 'egulated power suppl, 4%3%)# $> (read (oard $

CIRCI% I!$R!'


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'&E" $R!

f 1 I$..2 f 2 f (Hz)

va a< V =20m

+EOR':

In arlington connection of transistors" emitter of the first transistor is directl,connected to the *ase of the second transistor (ecause of direct coupling dc output current of the first stage is 4$h fe )I *$If arlington connection for n transitor is considered" then due todirect coupling the dc output current foe last stage is 4$h fe ) n times I *$ ue to ver, large

F"e56e7c8 97 +;< O6tp6t )!=ta>e 97 v!=t$< Ga7/ 2? =!>9)!@)7< 97 d,<

110

1001000

10000100000

10000001000000

0

1+01+0&1+10

2.72'175'5

4.715277.22614&&

7.245'406

7.254164'7.22120&

7.02'&61

5.551612&'

62.5150''

72.5'47&5

&2.50'45112

6

0.0'72'

0.2&1116

0.460&67

0.46441

0.46451

40.464'1

0.45226

70.'4647

&0.0571'

40.00600

'0.0005&

&


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amplification factor even two stage arlington connection has large output current and outputstage ma, have to *e a power stage !s the power amplifiers are not used in the amplifier circuitsit is not possi*le to use more than two transistors in the arlington connection

In arlington transistor connection" the lea?age current of the first transistor is amplified

*, the second transistor and overall lea?age current ma, *e high" 6hich is not desired

PROCEDURE:

$ Connect the circuit as per the circuit diagram

2 1et #i @% mv" using the signal generator

3

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