Spartan 3e

SPARTAN 3E DEVELOPMENT BOARD Model No : (VPTB - 05)

(Specially Designed for Polytechnic Syllabus - Kerala)

User Manual

Version 1.0

Technical Clarification /Suggestion :N / FTechnical Support Division,Vi Microsystems Pvt. Ltd.,Plot No :75, Electronics Estate,Perungudi, Chennai - 600 096, INDIA.Ph: 91- 44-2496 1842, 91-44-2496 1852Mail : [email protected],Web : www.vimicrosystem.com

CONTENTS

CHAPTER - 1 Introduction 1

CHAPTER - 2 Clock Source 4

CHAPTER - 3 Switches & LEDs 7

CHAPTER - 4 Character LCD Screen 8

CHAPTER - 5 RS232 Serial Port 9

CHAPTER - 6 PS/2 Mouse /Keyboard Port 10

CHAPTER - 7 Analog to Digital Converter & Digital To Analog Converter 12

CHAPTER - 8 PWM Generations 14

CHAPTER - 9 Connector Details 16

CHAPTER-10 VHDL Code for VPTB-05 18

CHAPTER-11 Add on Card Programs for VPTB - 05 Using Polytechnic Syllabus Kerala 42

EXPERIMENT - 1A Verilog Code for Basic Logic Gates in Dataflow Style of Modelling 42

EXPERIMENT - 1B Verilog Code for 4 To1 Multiplexer Using Behavioral Style of Modelling 44

EXPERIMENT - 1C Verilog Code for Decoder 3 to 8 Using Behavioral Modelling 46

EXPERIMENT -1D Verilog Code for Full Adder Using Data Flow Style of Modelling 49

EXPERIMENT -1E Verilog Code for 4 Bit Full Adder Using Structural Modelling 51

EXPERIMENT -1F Verilog Code for 4 Bit Magnitude Comparator Using Dataflow Modelling 54

EXPERIMENT -1G Verilog Code for Set Reset(SR)flip-flop in Data Flow Modeling 56

EXPERIMENT -1H Verilog Code for T Flip Flop Using Sync Reset Using Behavioral Modelling for FPGA Kit Implementation 58

EXPERIMENT -1I Verilog Code for Ripple Counter Using Structural Modellingfor FPGA Kit Implementation 61

EXPERIMENT -1J Verilog Code for Traffic Light Controller Using Behavioral Modelling 65

EXPERIMENT -1K Verilog Code for Bidirectional Switch Using Dataflow Modelling 69

EXPERIMENT -1L Verilog Code for Synchronous Counter with Clear and Count Enable Using Behavioral Modelling 71

SPARTAN 3E DEVELOPMENT BOARD VPTB - 05

Vi Microsystems Pvt. Ltd., [ 1 ]

CHAPTER - 1INTRODUCTION

The Vi Microsystems Spartan-3E Low Cost Kit is a demonstration platform intended for you tobecome familiar with the new features and availability of the Spartan-3E FPGA family. This Kitprovides a low-cost, easy-to-use development and evaluation platform for Spartan-3E FPGAdesigns.

KEY COMPONENTS AND FEATURES

Figure 1 shows the Spartan-3E Low Cost board block diagram, which includes the followingcomponents and features:

* 100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Packpackage (XC3S100E-TQ144)# 2,160 logic cell equivalents

# Four 18K-bit block RAMs (72K bits)

# Four 18x18 pipelined hardware multipliers

# Two Digital Clock Managers (DCMs)

* 32 Mbit Intel Strata Flash

* 3 numbers of 20 pin header to interface VLSI based experiment modules

* 8 input Dip Switches

* 8 output Light Emitting Diodes(LEDs)

* On Board programmable oscillator (3 to 200 MHz)

* 16x2 Alphanumeric LCD

* RS232 UART

* 4 Channel 8 Bit I2C based ADC & single Channel DAC

* PS/2 Keyboard/Mouse

* Prototyping area for user applications

* On Board configuration Flash PROM XCF01S



BLOCK DIAGRAM

Figure -1



POWERING UP THE BOARD FOR THE FIRST TIME

1. Connect Power to the Board

Refer Figure- 2

2. Initialize FPGA

a. Press power switch to apply power to the board

b. The Rolling lights,Rolling Display, Transmitting Spartan-3E Features Designsis automatically loaded into the FPGA from the Flash PROM and displayed on theLEDs, LCD & Serial Port.

Figure - 2



CHAPTER - 2

CLOCK SOURCESpartan3 FPGA works in different Clock frequencies. User can use any frequencies as givenbelow,

PLL Oscillator Settings

Default Factory settings = 20MHz

For PLL, ICS525-01 or ICS525-02 is used. Select the clock settings as per the PLL in theonboard

0 = Shorted1 = Open

ICS525-01 Clock Table Between 1 to 100 MHZ

Table -1

1MHz 3.6864MHZ 4MHz 20MHz 24MHz25.175MHz 48MHz 66MHz 80MHz 100MHz

S2S1S0R6R5R4R3R2R1R0

V8V7V6V5V4V3V2V1V0

0000101110

000000100

0000110001

000100111

0000001010

000000100

0100000010

000000100

1000000010

000000100

1111001010

100010111

0010000011

000000100

0010001000

000011001

0010000001

000000100

0010000001

000000111



For any other CLK frequency in between 1MHz to 100MHz use the following formula.

( VDW + 8)* CLK frequency = Input frequency 2

(RDW + 2)(OD)

Where,Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)VCO Divider Word (VDW) = 4 to 511 (0,1,2,3 are not permitted)Output Divider (OD) = Values below

EXAMPLE

To generate 12 MHz, assume Crystal + frequency or Input frequency is 20MHz.

In general, VDW + 8Clock Frequency = Input Frequency x 2 =

(RDW + 2) (OD)

4 + 8Clock Frequency = 20 MHz x 2 = 12 MHz

(18 + 2)(2)

ICS525-01 Output Divider and Maximum Output Frequency Table

Table:2

S2 S1 S0 CLK Max. Output Frequency (MHz)

Pin5 Pin4 Pin3 Output Divider VDD = 5V VDD = 3.3V0 - 70 C -40 to 85 C 0 - 70 C -40 to 85 C0 0 0 00 0 0 10 26 23 18 160 0 1 2 160 140 100 900 1 0 8 40 36 25 220 1 1 4 80 72 50 451 0 0 5 50 45 34 301 0 1 7 40 36 26 231 1 0 9 33.3 30 20 181 1 1 6 53 47 27 24

* VCO Divider Word (VDW) = V8 to V0 = 000000100 = 4 (Decimal);* Reference Divider Word (RDW) = R6 to R0 = 0010010 = 18 (Decimal);* Output Divider (OP) = 2 (from the table given above)



ICS525-02 Clock Table Between 3 MHZ TO 200 MHZ

Table : 3

3.6864MHZ 4MHz

20MHz

24MHz

25.175MHz

48MHz

66MHz

80MHz

100MHz

200MHz

S2S1S0R6R5R4R3R2R1R0

V8V7V6V5V4V3V2V1V0

0001010011

000100111

000000

1101

000000001

0100000000

000000000

1000000001

000000001

0100110111

100010111

1000000000

000000100

0010001000

000011001

0010000000

000000000

0010000000

000000010

1100000000

000000010

ICS525-02 Output Divider and Maximum Output Frequency Table:

Table : 4

S2 S1 S0 CLK Max Output Freqency (MHZ)

Pin5 Pin4 Pin3 Output DividerVDD=5V VDD=3.3V

-40 to 85C0 -40 to 85 C

0

0 0 0 6 67 400 0 1 2 200 1200 1 0 8 50 300 1 1 4 100 601 0 0 5 80 481 0 1 7 57 841 1 0 1 250 2001 1 1 3 133 80



CHAPTER - 3

SWITCHES & LEDs

Figure - 3Power Switch

The Spartan-3E Low Cost Kit has a slide power switch. Moving the power switch Up for PowerOn and down for power off.

Configuration Switch

The Spartan-3E Low Cost Kit has a push button Switch to Configure the FPGA from XilinxSerial Flash PROM.

Input Switches

The Spartan-3E Low Cost Kit has 8 way Dip switches for giving inputs to the FPGA i/o lines.

Dip Switch connections with FPGA

Switch Sw3(1) Sw3(2) Sw3(3) Sw3(4) Sw3(5) Sw3(6) Sw3(7) Sw3(8)

FPGAPin

p6 p18 p24 p36 p38 p41 p69 p78

Output LEDs

The Spartan-3E Low Cost Kit has 8 individual surface-mount LEDs. The LEDs are Labeled L3to L10.The cathode of each LED connects to ground. To light an individual LED, drive theassociated FPGA control signal High.

LED connections with FPGALED L3 L4 L5 L6 L7 L8 L9 L10

FPGAPin

p33 p34 p35 p39 p43 p44 p2 p50



CHAPTER - 4

CHARACTER LCD SCREENThe Spartan-3E Low Cost Kit prominently features a 2-line by 16-character liquid crystal display(LCD). The FPGA controls the LCD via the 8-bit data interface.

Figure - 4

Once mastered, the LCD is a practical way to display a variety of information using standardASCII and custom characters. However, these displays are not fast. Scrolling the display at half-second intervals tests the practical limit for clarity.

LCD Connections with FPGA

LCD D0 D1 D2 D3 D4 D5 D6 D7 RS DIOW

CS

FPGA Pin

p54 p58 p67 p68 p70 p74 p75 p76 p51 p52 p53

Voltage Compatibility

The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.However, theFPGAs output levels are recognized as valid Low or High logic levels by the LCD. The LCDcontroller accepts 5V TTL signal levels and the 3.3V LVC MOS outputs provided by the FPGAmeet the 5V TTL voltage level requirements.

The 390 series resistors on the data lines prevent over stressing on the FPGA and Strata FlashI/O pins when the character LCD drives a High logic value. The character LCD drives the datalines when LCD RW is High. Most applications treat the LCD as a write only peripheral andnever read from the display.



CHAPTER - 5

RS232 SERIAL PORT

Figure - 5

The Spartan 3E Low Cost board has one RS-232 serial port. The RS-232 transmit and receivesignals appear on the male DB9 connector, labeled as p8, indicated as in Figure -5. The connectoris a DTE-style serial port connector available on most personal computers and workstations. Usea standard straight-through serial cable to connect the board to the PCs serial port.

Serial port connections with FPGA

Serial signal TXD RXD RTS CTS

FPGA Pin p83 p82 p85 p86



CHAPTER - 6

PS/2 MOUSE/KEYBOARD PORTThe Spartan 3E Low Cost board includes a PS/2 mouse/keyboard port and the standard 6-pinmini-DIN connector, labeled p10 on the board. Figure - 6 shows the PS/2 connector, and belowtable shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a hostdevice, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data. Both amouse and keyboard drive the bus with identical signal timings and both use 11-bit words thatinclude a start, stop and odd parity bit. However, the data packets are organized differently fora mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfersso the host device can illuminate state LEDs on the keyboard.

PS2 Timing Waveform



Keyboard Scan Code

PS2 Signals with FPGA

PS2 SIGNAL PS2 CLK PS2 DATA

FPGA PIN p81 p77



CHAPTER - 7

ANALOG TO DIGITAL CONVERTER & DIGITAL TOANALOG CONVERTER

The Spartan-3E Low Cost Kit includes a PCF8591, 8 Bit 4 Channel I2C based Analog to DigitalConverter(ADC) and Single Channel Digital to Analog Converter(DAC) as shown in Figure-6.

Figure - 6

The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device withfour analog inputs, one analog output and a serial I2C-bus interface. Three address pins A0, A1and A2 are used for programming the hardware address, allowing the use of up to eight devicesconnected to the I2C-bus without additional hardware. Address, control and data to and from thedevice are transferred serially via the two-line bidirectional I2C-bus. The functions of the deviceinclude analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digitalconversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given bythe maximum speed of the I2C-bus.

Address Byte

Each PCF8591 device in an I2C-bus system is activated by sending a valid address to the device.The address consists of a fixed part and a programmable part. The programmable part must beset according to the address pins A0, A1 and A2.

MSB LSB

1 0 0 1 A2 A1 A0 __R/W

Fixed Part Programmable part



Control Byte

The second byte sent to a PCF8591 device will be stored in its control register and is requiredto control the device function.

PCF8591(ADC/DAC) Connections with FPGA

PCF8591 SIGNALS SCLK SDA

FPGA PIN p88 p87



CHAPTER - 8

PWM GENERATIONSPulse Width Modulation (PWM) is a technique to provide a logic 1" and logic 0" for acontrolled period of time. Pulse Width Modulation is used in many applications such ascontrolling the speed of a motor. This board also used for the same application as user needs.PWM output is terminated in the Box type header.

Pin Details

PWM Signals FPGA Pins

PWM1 P93

PWM 2 P94

PWM 3 P96

PWM 4 P97

PWM 5 P98

PWM 6 P103

PWM 7 P104

PWM 8 P105

Figure - 7

Translator Features

Translator device is used in-between FPGA I/O lines and Box type Header to translate 3.3V to5V and Vice-versa.

* Device used: SN74LVCC3245A

* Bidirectional Voltage Translator

* 2.3 V to 3.6 V on A Port and 3 V to 5.5 V on B Port

* Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage.



This 8-bit (octal) non inverting bus transceiver contains two separate supply rails. The B port isdesigned to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designedto track VCCA, which operates at 2.3V to 3.6 V. This allows for translation from a 3.3-V to a5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and viceversa.

The SN74LVCC3245A is designed for asynchronous communication between data buses. Thedevice transmits data from the A bus to the B bus or from the B bus to the A bus, depending onthe logic level at the direction-control (DIR) input. The output-enable (OE) input can be used todisable the device so the buses are effectively isolated.

Function Table

INPUTSOPERATION

__ OE DIR

L L B data to A bus

L H A data to B bus

H X Isolation

Translator used in this board to convert 3.3V to 5V or vice-versa. Selection of particulartranslator is to be achieved by the following signals,

Pin Details of Translator Selections

Terminations of DIR pins with FPGA

DIR SIGNAL OE1 DIR1

FPGA PINS P91 P92



CHAPTER - 9

CONNECTOR DETAILSThe Spartan-3E Low Cost Kit has three 20-pin connectors labeled as P2, P4 and P9 respectively.Connector P2 is on the top, P4 is on the left top and P9 is on the left bottom of the board.

20 Pin Connectors

Pin 20 on each connector is always GND. Similarly, pin 1 is always the output from the DCregulator. Depending upon the jumpers, 3.3V or 5V is selected. For P2 connector, to get 3.3VJP2" is short and JP1" is open or to get 5V JP1" is short and JP2" is open. For P4 connector,to get 3.3V JP6" is short and JP5" is open or to get 5V JP5" is short and JP6" is open. ForP6 connector, to get 3.3V JP11" is short and JP10" is open or to get 5V JP10" is short andJP11" is open.

Pin Detail for P2 Connector

SCHEMATICNAME

FPGAPIN CONNECTOR

FPGAPIN

SCHEMATICNAME

VCC - 1 2 P106 IO36

IO37 P10 3 4 P29 IO38

OE-* P91 5 6 P92 DIR*

SPWM1* P93 7 8 P94 SPWM2*

SPWM3* P96 9 10 P97 SPWM4*

SPWM5* P98 11 12 P103 SPWM6*

SPWM7* P104 13 14 P105 SPWM8*

M0 P62 15 16 P60 M1

IO39 P59 17 18 P63 DIN

CCLK P71 19 20 - GND

Note

1. If your are using * these pins, we can not use on board pwm that is P6 connector.2. If your using M0 & M1 in connector, after downloading the program remove the jumpers

M0, M1 & M2.




SCHEMATICNAME

FPGAPIN CONNECTOR

FPGAPIN

SCHEMATICNAME

VCC - 1 2 P86 SCTS

IO2 P140 3 4 P139 IO3

IO4 P135 5 6 P134 IO5

IO6 P132 7 8 P131 IO7

IO8 P130 9 10 P142 IO1

IO18 P112 11 12 P126 IO11

IO12 P125 13 14 P124 IO13

IO14 P123 15 16 P117 IO15

IO16 P116 17 18 P113 IO17

SRTS P85 19 20 - GND


SCHEMATICNAME

FPGAPIN CONNECTOR

FPGAPIN

SCHEMATICNAME

VCC - 1 2 P122 EXCLK

IO19 P32 3 4 P26 IO20

IO21 P25 5 6 P23 IO22

IO23 P22 7 8 P21 IO24

IO25 P20 9 10 P17 IO26

IO27 P16 11 12 P15 IO28

IO29 P14 13 14 P8 IO30

IO31 P7 15 16 P5 IO32

IO33 P4 17 18 P3 IO34

IO35 P2 19 20 - GND



CHAPTER - 10

VHDL CODE FOR VPTB - 051. SWITCH & LED

AIM:

Study of Switch and LED

FLOW CHART

VHDL Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity io isport ( sw:in std_logic_vector(7 downto 0); led:out std_logic_vector(7 downto 0));end io;architecture Behavioral of io isbeginled



UCF:

NET "sw" LOC = "p6" ;NET "sw" LOC = "p18" ;NET "sw" LOC = "p24" ;NET "sw" LOC = "p36" ;NET "sw" LOC = "p38" ;NET "sw" LOC = "p41" ;NET "sw" LOC = "p69" ;NET "sw" LOC = "p78" ;

NET "led" LOC = "p33" ;NET "led" LOC = "p34" ;NET "led" LOC = "p35" ;NET "led" LOC = "p39" ;NET "led" LOC = "p43" ;NET "led" LOC = "p44" ;NET "led" LOC = "p2" ;NET "led" LOC = "p50" ;



2. A/D CONVERTER

AIM:

Conversion of Analog data to Digital using I2C based ADC(PCF8591) and display the digitaldata in Led

System Clock = 20 MHz

FLOW CHART



VHDL Code:

--DEFAULT ANALOG INPUT IN CHANNEL 0.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity i2cadch0 is Port ( clk:in std_logic;

rst:in std_logic; sda:inout std_logic;

data:out std_logic_vector(7 downto 0); sclk:out std_logic );

end i2cadch0;

architecture Behavioral of i2cadch0 istype pcf is(set,write,read);signal adc:pcf; signal sig:std_logic_vector(4 downto 0);signal i:integer:=7;constant a_byte_w:std_logic_vector(7 downto 0):="10010000";Address Byteconstant a_byte_r:std_logic_vector(7 downto 0):="10010001";constant c_byte:std_logic_vector(7 downto 0):="01000000";Control Bytesignal clkdiv:std_logic;signal div:std_logic_vector(15 downto 0);begin--CLOCK DIVIDER PROCESSprocess(clk)beginif clk'event and clk='1' then

div

clkdiv

clkdiv

end case;end if;end process;process(clkdiv)variable j:std_logic_vector(7 downto 0):="00000000";



beginif clkdiv'event and clkdiv='1' thenif rst ='1' thensig '0');adc



sig(3 downto 0)



sclk

adcend case;

--A/D READ OPERATIONwhen read =>

sigsclk

if i > 0 theni



UCF:

NET "clk" LOC = "p56" ;NET "data" LOC = "p33" ;NET "data" LOC = "p34" ;NET "data" LOC = "p35" ;NET "data" LOC = "p39" ;NET "data" LOC = "p43" ;NET "data" LOC = "p44" ;NET "data" LOC = "p2" ;NET "data" LOC = "p50" ;NET "sclk" LOC = "p88" ;NET "sda" LOC = "p87" ;NET "rst" LOC = "p6" ;



3. D/A CONVERTER

AIM:

Generation of Square Wave using I C Based DAC(PCF8591)2


FLOW CHART

VHDL Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity square is Port ( sclk:out std_logic;

rst:in std_logic; clk:in std_logic; sda:out std_logic );end square;



architecture Behavioral of square issignal sig:std_logic_vector(4 downto 0);signal div:std_logic_vector(15 downto 0);signal data:std_logic_vector(7 downto 0);signal i:integer:=7;signal j:integer:=1;signal clkdiv:std_logic;constant a_byte_w:std_logic_vector(7 downto 0):="10010000";

--(1 0 0 1 A2 A1 A0 R/W) ADDRESS BYTEconstant c_byte:std_logic_vector(7 downto 0):="01000000";--CONTROL BYTEconstant datah:std_logic_vector(7 downto 0):="11111111"; --DIGITAL DATAconstant datal:std_logic_vector(7 downto 0):="00000000"; --DIGITAL DATAbegin--CLOCK DIVIDER PROCESSprocess(clk)beginif clk'event and clk='1' then

div clkdiv clkdiv end case;

end if;end process;--MAIN PROCESSprocess(clkdiv)beginif rst='1' then

sig '0');i



i sda



sclk sclk 0 then i



4. LCD DISPLAY

AIM:

To Display Characters in LCD


FLOW CHART

VHDL Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd isport(rs,cs,diow : inout std_logic;

clk : in std_logic;d : inout std_logic_vector(7 downto 0));

end lcd;architecture arch_lcd of lcd istype main1 is array(1 to 5) of std_logic_vector(7 downto 0);signal state1:main1:=(x"38",x"06",x"01",x"0f",x"80");type main2 is array(1 to 8) of std_logic_vector(7 downto 0);signal state2:main2:=(x"56",x"49",x"20",x"4d",x"49",x"43",x"52",x"4f");signal sig : std_logic_vector(29 downto 0) := "000000000000000000000000000000";signal i,j:integer:=1;beginprocessbegin



wait until clk'event and clk='1';sig rs



5. PS/2 KEYBOARD

AIM:

Read the Scan Code from PS/2 Keyboard and Display in Led

System Clock = 20MHz

FLOW CHART

VHDL Code:

LIBRARY ieee;USE ieee.std_logic_1164.ALL; Entity PS2SIMPL is Port ( Clk : In std_logic; Reset : In std_logic; PS2_Data : In std_logic; PS2_Clk : In std_logic; LEDdis : Out std_logic_vector (7 downto 0));end PS2SIMPL; Architecture SCHEMATIC of PS2SIMPL is component PS2_CTRL generic (FilterSize : positive := 8); port( Clk : in std_logic; -- System Clock Reset : in std_logic; -- System Reset PS2_Clk : in std_logic; -- Keyboard Clock Line PS2_Data : in std_logic; -- Keyboard Data Line



Scan_Code: out std_logic_vector(7 downto 0)-- Eight bits Data Out );

end component;signal gnd,Vcc : std_logic;signal Code : std_logic_vector (7 downto 0);begin Gnd Clk,Reset=>Reset,PS2_Clk=>PS2_Clk,

PS2_Data=>PS2_Data,Scan_Code=>leddis);end SCHEMATIC;

library IEEE;use IEEE.Std_Logic_1164.all;use IEEE.Numeric_Std.all;Entity PS2_Ctrl is generic (FilterSize : positive := 8); port( Clk : in std_logic; -- System Clock Reset : in std_logic; -- System Reset PS2_Clk : in std_logic; -- Keyboard Clock Line PS2_Data : in std_logic; -- Keyboard Data Line Scan_Code: out std_logic_vector(7 downto 0));-- Eight bits Data Outend PS2_Ctrl;Architecture ALSE_RTL of PS2_Ctrl issignal PS2_Datr : std_logic;subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);signal Filter : Filter_t;signal Fall_Clk : std_logic;signal Bit_Cnt : unsigned (3 downto 0);signal Scan_DAVi : std_logic;signal S_Reg : std_logic_vector(8 downto 0);signal PS2_Clk_f : std_logic; Type State_t is (Idle, Shifting); signal State : State_t;beginprocess (Clk,Reset)begin if Reset='1' then PS2_Datr



Fall_Clk State



UCF:

NET "Clk" LOC = "p56";NET "LEDdis" LOC = "p50";NET "LEDdis" LOC = "p2";NET "LEDdis" LOC = "p44";NET "LEDdis" LOC = "p43";NET "LEDdis" LOC = "p39";NET "LEDdis" LOC = "p35";NET "LEDdis" LOC = "p34";NET "LEDdis" LOC = "p33";NET "PS2_Clk" LOC = "p81";NET "PS2_Data" LOC = "p77";NET "Reset" LOC = "p6";



6. UART

AIM:

Implementation of UART and verify by Receving the data through Rx line and Transmitting thedata through Tx line


FLOW CHART

VHDL Code

TOP Unitlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all; entity usart is Port ( SysClk : in Std_Logic; -- System Clock

TxD : out Std_Logic; -- Tx output (serial data) RxD : in Std_Logic; -- Receiver input (serial data) );

end usart;architecture Behavioral of usart is signal EnabTx : Std_Logic; -- Enable TX unit signal EnabRx : Std_Logic; -- Enable RX unit signal temp : Std_Logic_vector(7 downto 0);-- Baud rate Generator



component ClkUnit port (SysClk : in Std_Logic; -- System Clock clkdiv26 : inout std_logic; -- Control signal used for Rx enable EnableTx : out Std_Logic); -- Control signal used for Tx enableend component;component txasync is port ( Clk : in Std_Logic; -- Clock signal Enable : in Std_Logic; -- Enable input

TxD : out Std_Logic; -- RS-232 data outputDataout : in Std_Logic_Vector(7 downto 0)-- parallel input

);end component;component rxasync port ( Clk : in Std_Logic; -- system clock signal Enable : in Std_Logic; -- Enable input RxD : in Std_Logic; -- RS-232 data input DataIn : out Std_Logic_Vector(7 downto 0)-- parallel output

);end component;beginClkDiv : ClkUnit

port map (SysClk,EnabRX,EnabTX); TxDev : txasync

port map (Sysclk,EnabTX,TxD,temp);RxDev :rxasync

port map (Sysclk,EnabRX,RxD,temp); end Behavioral;

--Clk Divider Unit:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity ClkUnit is port ( SysClk : in Std_Logic; -- System Clock 4 MHZ clkdiv26 : inout std_logic; -- Control signal for Rx

EnableTx : out Std_Logic -- Control signal for Tx );

end entity;

architecture Behaviour of ClkUnit issignal CntOne : std_logic_vector(4 downto 0) := "00001";signal Cnt26 : std_logic_vector(7 downto 0);



signal Cnt10 : std_logic_vector(4 downto 0);begin-- Divides the system clock of 20 MHz by 26 FOR RX TO GET 155 KHZ --DivClk26 : process(SysClk)beginif Rising_Edge(SysClk) then

Cnt26 -- divide 20 MHZ by 26 to get 155 KHZ ClkDiv26



TxD : out Std_Logic; -- RS-232 data output Dataout : in Std_Logic_Vector(7 downto 0));-- parallel output

end entity;architecture Behaviour of txasync issignal TReg : Std_Logic_Vector(7 downto 0); -- transmit registersignal BitCnt : std_logic_vector(4 downto 0); -- bit countersignal tmpTRegE : Std_Logic; -- High for Temp Tx register empty signal CntOne : std_logic_vector(4 downto 0):="00010";type main is (s1,s2);signal state:main; beginprocess(Clk,Enable,TReg)beginif Rising_Edge(Clk) thencase state iswhen s1 => if Enable = '1' then

TReg



--Receiver Unit

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity rxasync is port (Clk : in Std_Logic; -- system clock signal Enable : in Std_Logic; -- Enable input RxD : in Std_Logic; -- RS-232 data input DataIn : out Std_Logic_Vector(7 downto 0)-- parallel output

);end entity; architecture Behaviour of rxasync issignal Start : Std_Logic; -- Syncro signalsignal tmpRxD : Std_Logic; -- RxD buffersignal tmpDRdy : Std_Logic; -- Data ready buffersignal BitCnt : std_logic_vector(3 downto 0);signal SampleCnt : std_logic_vector(3 downto 0); -- samples on one bit countersignal ShtReg : Std_Logic_Vector(7 downto 0);signal DOut : Std_Logic_Vector(7 downto 0);signal tmpBitCnt : Integer range 0 to 15;signal tmpSampleCnt : Integer range 0 to 15;signal CntOne : std_logic_vector(3 downto 0):="0001";

begin

RcvProc : process(Clk,RxD,Enable)beginif Rising_Edge(Clk) then

tmpBitCnt



when 0 => if tmpRxD = '1' then -- Start Bit Start



CHAPTER - 11ADD ON CARD PROGRAMS FOR VPTB - 05 USING POLYTECHNIC

SYLLABUS KERALA

Exp - 1a Verilog code for basic logic gates in dataflow style of modelling

Module basicgates(andgate,orgate,notgate,nandgate,norgate,xorgate,xnorgate,a,b); //module declaration with inpu,output list

output and gate, orgate, notgate, nandgate, norgate, xorgate, xnorgate; //output declarationinput a, b; //input declaration//expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net.//Statements using the assign keyword are executed at the same time.assign andgate = a & b; assign orgate = a | b; assign notgate = ~a; assign nandgate = ~(a & b); assign norgate = ~(a | b); assign xorgate = a ^ b; assign xnorgate = a ~^ b;

end module

User Constraint File

NET "a" LOC = "p6"; NET "b" LOC = "p18"; NET "andgate" LOC = "p33"; NET "orgate" LOC = "p34"; NET "notgate" LOC = "p35"; NET "nandgate" LOC = "p39"; NET "norgate" LOC = "p43"; NET "xorgate" LOC = "p44"; NET "xnorgate" LOC = "p2";



ISE Xilinx Test Bench Waveform Result



Exp - 1b) Verilog code for 4 to1 multiplexer using behavioral style of modelling

module mux4x1(muxout,i0,i1,i2,i3,sel1,sel0);//module declaration with list of input,outputsoutput muxout; //output declarationinput i0,i1,i2,i3;//input declarationinput sel1,sel0;//input declarationreg muxout;//register declaration//All variables on the LHS of the always block must be declared as register using keyword reg//In verilog register represents data storage elements.//Statements within always block are executed sequentially.always @ (sel1 or sel0 or i0 or i1 or i2 or i3) begincase({sel1,sel0})2'b00 : muxout = i0; // 1 input assigned to muxout for select value "00"2'b01 : muxout = i1; // 2 input assigned to muxout for select value "01"2'b10 : muxout = i2; // 3 input assigned to muxout for select value "10"2'b11 : muxout = i3; // 4 input assigned to muxout for select value "11"endcaseend end module


#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin AssignmentsNET "i3" LOC = "p41" ;NET "i2" LOC = "p38" ;NET "i1" LOC = "p36" ;NET "i0" LOC = "p24" ;NET "muxout" LOC = "p33" ;NET "sel0" LOC = "p18" ;NET "sel1" LOC = "p6" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE



Exp - 1c) Verilog code for decoder 3 to 8 using behavioral modelling

// decoder has n inputs 2 power n outputs

module decoder3to8(oup,inp,en); //module declaration with i/p ,o/p listoutput [7:0] oup; //output declarationinput [2:0] inp; //input declarationinput en; ////input declarationreg [7:0] oup; //register declaration

always @ (inp or en) //when any one of the inputs in sensitivity list changes always //block is executed

begin

if (en) //enable is equal to 1 statements within begin end block is executed.hence enable //acts as control signal

begincase (inp) // output value is assigned with respect to the input as per truth table

//of the decoder 3'b000 : oup = 8'b00000001; 3'b001 : oup = 8'b00000010; 3'b010 : oup = 8'b00000100; 3'b011 : oup = 8'b00001000; 3'b100 : oup = 8'b00010000; 3'b101 : oup = 8'b00100000; 3'b110 : oup = 8'b01000000; 3'b111 : oup = 8'b10000000; default: oup = 8'b00000000; //default statement is optionalendcase

end else

oup = 8'b00000000; // when enable is 0 output is 0.hence decoder is disabledend end module





#PACE: Start of PACE I/O Pin AssignmentsNET "en" LOC = "p6" ;NET "inp" LOC = "p36" ;NET "inp" LOC = "p24" ;NET "inp" LOC = "p18" ;NET"oup" LOC = "p50";NET "oup" LOC = "p2" ;NET "oup" LOC = "p44" ;NET "oup" LOC = "p43" ;NET "oup" LOC = "p39" ;NET "oup" LOC = "p35" ;NET "oup" LOC = "p34" ;NET "oup" LOC = "p33" ;






Exp - 1d) Verilog code for full adder using data flow style of modelling

Module fulladder(sum,carry,a,b,cin); //module declaration with i/p ,o/p listoutput sum,carry; //output declaration input a,b,cin; //input declaration

//expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net.Statements using the assign keyword are executed at the same time.

assign sum = a ^ b ^ cin; //sum output is evaluvated based on a xor b xor cinassign carry = (a & b)|(b & cin)|(a & cin); //carry output based on a.b + b.cin+a.cin

end module



#PACE: Start of PACE I/O Pin AssignmentsNET "a" LOC = "p6" ;NET "b" LOC = "p18" ;NET "carry" LOC = "p35" ;NET "cin" LOC = "p24" ;NET "sum" LOC = "p33" ;






Exp -1 e) Verilog code for 4 bit full adder using structural modelling

//structral modelling is the gate level modelling using primitive gates such as// and,or,not,nand ...

module fulladder4b(sum,cout,a,b); //module declaration with input,output listoutput [3 :0]sum; //output declaration for sum outputoutput cout; //output declaration for carry outputinput [3 :0]a,b; //input declaration for a,b inputs

wire c1,c2,c3; //wire declaration for internal connections in a logic circuit which do //not store values but pass the values from one end to other end.

//here the value of cin input to the 4 bit full adder is given at the instantiation itself as //1'b0 at fa0.the user can change the value of carry in ie,cin by replacing 1'b0 as 1'b1 in //fa0

fulladd fa0(sum[0],c1,a[0],b[0],1'b0); //full adder instantiationfulladd fa1(sum[1],c2,a[1],b[1],c1); fulladd fa2(sum[2],c3,a[2],b[2],c2); fulladd fa3(sum[3],cout,a[3],b[3],c3);

endmodule

module fulladd(sum,carry,a,b,c);output sum,carry;input a,b,c;wire axorb,aandb,bandc,aandc;

xor halfsum(axorb,a,b);xor fullsum(sum,axorb,c);and a1(aandb,a,b);and a2(bandc,b,c);and a3(aandc,a,c);or o1(carry,aandb,bandc,aandc);

endmodule




NET "a" LOC = "p6";NET "a" LOC = "p18";NET "a" LOC = "p24";NET "a" LOC = "p36";NET "b" LOC = "p38";NET "b" LOC = "p41";NET "b" LOC = "p69";NET "b" LOC = "p78";NET "sum" LOC = "p33";NET "sum" LOC = "p34";NET "sum" LOC = "p35";NET "sum" LOC = "p39";NET "cout" LOC = "p44";



Exp -1 f) Verilog code for 4 bit magnitude comparator using dataflow modelling

module magcomp(a,b,equal,greater,lesser); //module declaration with i/p,o/p list input [3:0]a; //comparator input declaration input [3:0] b; //comparator input declaration output equal; //comparator output declaration for a equal to b output greater; //comparator output declaration for a greater than b output lesser; //comparator output declaration for a less than b

// for checking equality for the two inputs all inputs of a have to be exnor'ed with b input. // since xnor output is high when i/ps are same and low when they differ.

assign x3 = a[3] ~^ b[3]; assign x2 = a[2] ~^ b[2]; assign x1 = a[1] ~^ b[1]; assign x0 = a[0] ~^ b[0];

// for equality condition:

assign equal = (x3 & x2 & x1 & x0 ); // 1 led glows for a = b condition.

// when x3,x2,x1,x0 are given to an and gate the output is high when all(ie,x3,x2,x1,x0 are// equal to 1 which means a equal to b.and gate output is low when any one of x3,x2,x1,x0 is low(ie,'0') which means a not equal to b).

//for greater than condition :// the boolean expression given below has to be verified

assign greater = ((a[3] & (~b[3])) | (x3 & a[2] & (~b[2])) | (x3 & x2 & a[1] & (~b[1])) | (x3 & x2 & x1 & a[0] & (~b[0]))); // the above exp is continued here

//2 led glows for a > b

//for lesser than condition :// the boolean expression given below has to be verified

assign lesser = ((b[3] & (~a[3])) | (x3 & b[2] & (~a[2])) | (x3 & x2 & b[1] & (~a[1])) |(x3 & x2 & x1 & b[0] & (~a[0]))); // the above exp is continued here

//3 led glows for a < b

end module





#PACE: Start of PACE I/O Pin AssignmentsNET "a[0]" LOC = "p36" ;NET "a[1]" LOC = "p24" ;NET "a[2]" LOC = "p18" ;NET "a[3]" LOC = "p6" ;NET "b[0]" LOC = "p78" ;NET "b[1]" LOC = "p69" ;NET "b[2]" LOC = "p41" ;NET "b[3]" LOC = "p38" ;NET "equal" LOC = "p33" ;NET "greater" LOC = "p34" ;NET "lesser" LOC = "p35" ;






Exp -1 g) Verilog code for Set Reset(SR)flip-flop in data flow modeling

module srff(q,qbar,clk,s,r); //module declarationoutput q,qbar; //srff outputs declarationinput clk,s,r; //srff inputs declarationwire nand1,nand2,nand3,nand4,nand5,nand6,notclk; //declare internal connections as wire//expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net.//Statements using the assign keyword are executed at the same time.

assign nand1 = ~(s & clk); //nand operation of s ,clkassign nand2 = ~(r & clk); //nand operation of r ,clkassign nand3 = ~(nand1 & nand4); //nand operation of nand1,nand4assign nand4 = ~(nand3 & nand2); //nand operation of nand3,nand2assign notclk = ~clk; // not operation of clk assign nand5 = ~(nand3 & notclk); //nand operation of nand3,notclkassign nand6 = ~(nand4 & notclk); //nand operation of nand4,notclkassign q = ~(nand5 & qbar); //nand operation of nand5,qassign qbar = ~(nand6 & q); //nand operation of nand6,qbar end module



#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p56" ;NET "q" LOC = "p33" ;NET "qbar" LOC = "p34" ;NET "r" LOC = "p18" ;NET "s" LOC = "p6" ;






Exp 1h) Verilog code for T FLIP FLOP using sync reset using behavioral modellingfor FPGA kit implementationmodule tff(t,clk,reset,out,out1); //Input Portsinput t, clk, reset ; output out,out1; //Output Ports//All variables on the LHS of the always block must be declared as register using keyword reg//In verilog register represents data storage elements.//Statements within always block are executed sequentially.

reg q,qbar,clkslw;reg [28 : 0] count1;

//slow clock generation with count block

always @ (posedge clk) if (count1 !== 8388608)

count1




#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "clk" LOC = "p56" ;NET "out" LOC = "p33" ;NET "out1" LOC = "p34";NET "reset" LOC = "p6" ;NET "t" LOC = "p18" ;

#PACE: Start of PACE Area Constraints#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACE

Exp 1h) Verilog code for T FLIP FLOP using sync reset using behavioral modelling without slow clock for test bench

module tff(t,clk,reset,out,out1); input t, clk, reset ; //Input Portsoutput out,out1; //Output Ports

//All variables on the LHS of the always block must be declared as register using keyword reg//In verilog register represents data storage elements.//Statements within always block are executed sequentially.

reg q;

//Code for TFF Starts Here

always @ (posedge clk)

if (~reset) //means when reset is zero ie,active low q



Exp 1 i) Verilog code for ripple counter using structural modelling f o r F P G A k i timplementation module ripple(clk, count, clear);input clk, clear;output [3:0] count;wire [3:0] count, countbar;reg [28 : 0] count1;reg clkslw;wire clk1;//slow clock generation// count blockalways @ (posedge clk) if (count1 !== 8388608)

count1



module dreg_async_reset (clk, clear, d, q, qbar);input d, clk, clear;output q, qbar;reg q;always @ (posedge clk or negedge clear)beginif (!clear)q



Exp 1 j) Verilog code for traffic light controller using behavioral modelling

`timescale 1ns / 1ps// SYSTEM CLOCK FREQUENCY IS 20 MHZ//Connect P3 (TLC) TO P4 (VPTB-05)//Connect P2 (TLC) TO P9 (VPTB-05)//Connect 20 core parallel port cable from PC's parallel port to the JTAG connector of VPTB-05//Close JP5 & JP10 in VPTB-05

module traffic(clk, reset, p1, p2, p3, p4, pl); //module declarationinput clk; // input clock declarationinput reset; // input reset declarationoutput [4:0] p1; // output declaration for road1output [4:0] p2; // output declaration for road2output [4:0] p3; // output declaration for road3output [4:0] p4; // output declaration for road4output [3:0] pl; // output declaration for pedestrian crossing// constant declarationsparameter green = 8'h47; // for displaying the character G the ascii value is 47 in hexparameter red = 8'h52; // for displaying the character R the ascii value is 52 in hexparameter yellow = 8'h59;// for displaying the character Y the ascii value is 59 in hex

reg [7:0] path1; //register declaration for road1reg [7:0] path2; //register declaration for road2reg [7:0] path3; //register declaration for road3reg [7:0] path4; //register declaration for road4reg [7:0] ped; //register declaration for pedestrian crossing

reg [30:0]sig; always @ (posedge clk )

if (reset == 1'b0) //at reset conditionbeginpath1



sig



path2




NET "clk" LOC = "p56"; NET "reset" LOC = "p6";NET "p1" LOC = "p32"; # 1 p9-3NET "p1" LOC = "p25"; # 2 p9-5NET "p1" LOC = "p22"; # 3 p9-7NET "p1" LOC = "p20"; # 4 p9-9NET "p1" LOC = "p16"; # 5 p9-11NET "p2" LOC = "p14"; # 6 p9-13NET "p2" LOC = "p7"; # 7 p9-15NET "p2" LOC = "p4"; # 8 p9-17NET "p2" LOC = "p17"; # 17 p9-10NET "p2" LOC = "p15"; # 18 p9-12NET "p3" LOC = "p8"; # 19 p9-14NET "p3" LOC = "p5"; # 20 p9-16NET "p3" LOC = "p3"; # 21 p9-18NET "p3" LOC = "p139";# 22 p4-4NET "p3" LOC = "p134";# 23 p4-6NET "p4" LOC = "p131";# 24 p4-8NET "p4" LOC = "p112";# 13 p4-11NET "p4" LOC = "p26"; # 14 p9-4NET "p4" LOC = "p23"; # 15 p9-6NET "p4" LOC = "p21"; # 16 p9-8NET "pl" LOC = "p140";# 9 p4-3NET "pl" LOC = "p135";# 10 p4-5NET "pl" LOC = "p132";# 11 p4-7NET "pl" LOC = "p130";# 12 p4-9



Exp 1k) Verilog code for bidirectional switch using dataflow modelling

module bidir(bidi,en,sw,led);

inout bidi; // inout ie, input as well as output(bidirectional) input en; // input declaration for enable input sw; // input declaration for switch output led; //output declaration for led //expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net.//Statements using the assign keyword are executed at the same time.

assign bidi = en ? sw : 1'bz; //when enable input ie en is 1 bidi acts as output and// when en is 0 the bidi is tristated which means it is ready to receive// input from external environment.

assign led = bidi; // the value at bidi is always displayed in led. i.e when it // acts as a output the value at bidi is displayed in led // similarly when bidi acts as input , the value at input is displayed in led L3

endmodule



#PACE: Start of PACE I/O Pin AssignmentsNET "bidi" LOC = "p59" ;NET "en" loc = "p6";NET "sw" LOC = "p18" ;NET "led" LOC = "p33" ;






Exp 1 l) Verilog code for synchronous counter with clear and count enable usingbehavioral modelling

module syncntr4bit(out,enable,clk,reset); //module declaration//Output Portsoutput [3:0] out; // Output of the counter//Input Portsinput enable, clk, reset; // enable input, clock input, reset input for counter//Internal Variables

reg clkslw;reg [28 : 0] count1;reg [3 : 0] out;

//slow clock generation - count blockalways @ (posedge clk) if (count1 !== 8388608)

count1




NET "clk" LOC = "p56";NET "enable" LOC = "p18";NET "out" LOC = "p33";NET "out" LOC = "p34";NET "out" LOC = "p35";NET "out" LOC = "p39";NET "reset" LOC = "p6";




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