UVM Presentation Santhosh

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    Universal Verifcation

    Methodology

    Santosh

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    Introduction

    UVM provides the best rameor! toachieve coverage"driven verifcation#C$V%

     &he purpose o C$V is to'◦  (liminate the e)ort and time spent

    creating hundreds o tests.

    ◦  (nsure thorough verifcation using up"

    ront goal setting.◦  *eceive early error notifcations and

    deploy run"time chec!ing and erroranalysis to simpliy debugging.

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     &ypical Verifcation(nvironment

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    UVM Class +ierarchy

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    UVM ,ase ClassesUvm-obect

    Set o methods or such common operations as create/copy/ compare/ print and record.

    *oot ,ase class or all obects in uvm environment

    Uvm-transaction *oot base class or all UVM transactions.

    Inheriting rom uvm-obect and adds timing 0 recordinginterace.

    Uvm-report-obect Provides reporting acility.

    Components can issue various messages ith di)erentseverity levels

    Confgurable actions or individual messages rom aparticular component or or all messages rom allcomponents in the environment.

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    UVM ,ase Classes#cont2d%

    Uvm-component Inherits all eatures o uvm-obect/

    uvm-reporting-class

    Provides interaces li!e hierarchy/phasing/ reporting/ transaction recording/actory

    Uvm-root

    Implicit top"level and phase controller orall UVM components

    3n instance is automatically created

    Supports other eatures li!e Searching

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    UVM 4actory◦ Used to manuacture #create% UVM obects and

    components.

    ◦ User defned obects and components are to beregistered ith the actory by macros uvm-component-registry 5#&/&name%

    uvm-obect-registry 5#&/&name%

    ◦ &he actory generates and stores lighteightpro6ies to the user"defned obects or e7cientusage o Memory

    Construction ' obects and components registeredith actory are created using Create#%

    ◦ 8verriding ' 3ll instances 9 types can be overridenusing methods o actory.

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    Classes derived romuvm-componentUvm-test

    Class to defne all test"cases

     &hese class names acts as inputs to run-test#%

    Uvm-driver Ports to connect se:uencer

     &as!s to drive signals onto $U&

    uvm-monitor Connected to $U& or monitoring signals

    Connected to analysis ports

    Uvm-agentUvm-envuvm-se:uencer

    serves as an arbiter or controlling transaction ;o rommultiple stimulus generators

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    Classes derived romuvm-transaction

     &he uvm-se:uence-base class provides theinteraces needed to create streams o se:uencesuch as pre-body/ body/ post-body etc./

    Uvm-se:uence is the base class or all userdefned se:uences

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    Se:uencers

    uvm-se:uencer 5#*(

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    Se:uencer = $river Interace

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    Se:uence = $riverinterace

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    UVM *eporting  Ex: virtual function void uvm-report-ino

    #string id/string message/int verbosity>UVM-M($IUM/string flename>??/int line>@%

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     &ransaction Core utilities

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    4ield 3utomation 4lags

    (6ample or registering transaction obect 'Auvm-obect-utils-begin#Pac!et%

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    UVM PhasesBe

    Creates obects/ basic initialiEation is done

    ,uild Confguration parameters are applied in creating child classes

    3ll component hich are constructed using Create unction are created

    Connect Components are connected using &LM ports 3ll ,inding Processes all port/ e6port/ and imp connections Chec!s hether each port2s min and ma6 connection re:uirements are

    met

    (nd o (laboration

    8verride this method to perorm any chec!s on the elaboratedhierarchy beore the simulation phases begin

    Start o Simulation 8verride this method to perorm component" specifc pre"run

    operations/ such as discovery o the elaborated hierarchy/ printingbanners/ etc.

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    UVM Phases #Cont2d%

    *un Main body o the test is e6ecuted here all

    threads are or!ed o) 

    (6tract 3ll the re:uired inormation is gathered

    Chec! Chec! the results o the e6tracted inormation

    such as un responded re:uests in scoreboard/

    read statistics registers etc*eport

    *eporting pass9ail status.

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    Ubus (6ample

     Ubus is a basic bus arbiter ithpriority

    Fiven e6ample $U& supports G

    master ith @ having priorityover H

     &est"bench is designed or

    confgurable number o masterand slave agents/ confgurablecoverage and chec!s

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    Verifcation (nvironment

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    Protocol Phases

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    ◦ $efne a transaction pac!et hich e6tends rom uvm-se:uence-item

    ◦ $efne Interace or signal onto $U&

    $efne Master agentMaster $river

    Master MonitorMaster Se:uencer

    $efne Slave agentSlave $riverSlave MonitorSlave Se:uencer

    ◦ (nvironment Create an environment ith given

    parameters

    ◦ Scoreboard

    ◦ &est"case 8bects o environment and scoreboard are

    created/ and connected

    3 &est is run by selecting single9multiplese:uences to generate the stimulus

    $efne ,us Monitor

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