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VT82885

Real Time ClockVIA Technologies, Inc.

FEATURES

Drop-in replacement for IBM AT computerclock/calendar.

Pin configuration closely matches theDS12887, DS12885and DS12885Q

Counts seconds, minutes, hours, days,day of the week, date, month, and yearwith leap year compensation

Binary or BCD representation of time,calendar and alarm

12- or 24-hour clock with AM and PM in12-hour mode

Daylight Savings Time option

Intel bus timing

Multiplex bus for pin efficiency

Interfaced with software as 128 RAMlocations

- 14 bytes of clock and control registers- 114 bytes of general purpose RAM

Programmable square wave output signal

Bus-compatible interrupt signals (IRQ#)

Three interrpts are separately software-maskable and testable

- Times-of-day alarm once/second toonce/day

- Periodic rates from 122 s to 500 ms- End of clock update cycle

Optional 28-pin PLCC surface mountpackage

DESCRIPTION

The VT82885 Real Time Clock is designedto be a direct replacement for the DS12885.The VT82885 is identical in form, fit andfunction to the DS12885. It has 114 bytes of

general purpose RAM. Access to this RAMspace is determined by the logic levelpresented on AD6 during the addressportion of an access cycle. An externalcrystal and battery are the only componentsrequired to maintain time-of-day andmemory status in the absence of power. Acomplete description of operating conditions,

electrical characteristics, bus timing and pindescriptions follows.

PIN ASSIGNMENT

1

2

GND

3

4

5

X1

X2

AD0

AD1

24 VCC

23

22

21

20

19

18

17

SQW

NC

RCLR#

VBAT

IRQ#

RESET#

RD#

6

7

8

AD2

AD3

AD4

AD5

AD6

AD7

GND

9

10

11

12

16

15

14

13

NC

WR#

AS

CS#

VT82885 24 PIN DIP

AD0

AD1

AD2

AD3

AD4

AD5

NC

RCLR#

VBAT

IRQ#

RESET#

RD#

GND

WR#

X

2

X

1

G

N

D

N

C

V

CC

S

Q

W

N

C

A

D6

N

C

A

D7

G

ND

C

S#

A

S

N

C

12

7

6

3

9

8

10

13 14 15 16 17

20

21

22

23

24

2728

25

11 19

18

4 26

5

VT82885 28-PIN PLCC

PIN DESCRIPTION

AD0-AD7 - Multiplexed Address/Data BusNC - No ConnectionCS# - Chip SelectAS - Address Strobe

loaded from Elcodis.comelectronic components distributor
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WR# - Write StrobeRD# - Read StrobeRESET# - Reset InputIRQ# - Interrupt Request OutputSQW - Square Wave Output

VCC - +5 Volt Supply

GND - GroundX1, X2 - 32.768 kHz Crystal Connec-

tionsVBAT# - +3 Volt Battery InputRCLR# - RAM Clear

OPERATION

The block diagram in Figure 1 shows thepin connections with the major internal func-

tions of the VT82885. The following para-graphs describe the function of each pin.

FIQURE 1: BLOCK DIAGRAM VT82885

POWER-DOWN/POWER-UPCONSIDERATIONS

The Real Time Clock function will continueto operate and all of the RAM, time, calen-dar and alarm memory locations remainnonvolatile regardless of the level of the VCC

input. When VCC is applied to the VT82885and reaches a level of greater than 4.25volts, the device becomes ac-cessible after100 ms, provided that the oscillator isrunning and the oscillator countdown chainis not in reset (see Register A). This timeperiod allows the system to stabilize after

OSC +8 +64 +64

PERIODIC INTERUPT SQUARE WAVESELECTOR

SQUAREWAVE OUT

POWERSWITCHAND

WRITEPROTECT

BUSINTERFACE

CLOCK/CALENDAR

UPDATE

BCD/BINARY

INCREMENT

REGISTERS A,B,C,D

CLOCK, CALENDAR

AND ALARM RAM

USER RAM114 BYTES

X2

X1

GND

AS

RD#

AD0-AD7

WR#

VBAT

VCC

CS#

CS#

SQW

IRQ#

RESET#

RCLR#

POK

VCC


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power is applied. When VCC falls below 4.25volts, the chip select input is internally forcedto an inac-tive level regardless of the valueof CS# at the input pin. The VT82885 is,therefore, write-protected. When VCC falls

below the level of VBAT, the external VCCsupply is switched off and the external VBATlithium energy source supplies power to theReal Time Clock and the RAM memory.

SIGNAL DESCRIPTIONS

VCC DC power is provided to the device onthIs pin. VCC is the +5 volt input. When 5volts are applied within normal limits, thedevice is fully accessible and data can bewritten and read. When VCC is below 4.25volts typical, reads and writes are inhibited.However, the timekeeping function contin-ues unaffected by the lower input voltage. As

VCC falls below VBAT, the RAM andtimekeeper are switched over to the exter-nal lithium energy source. The timekeeping

function maintains an accuracy of 1 minute

per month at 25C regardless of the voltageinput on the VCC pin.

VBAT Battery input for any standard 3 voltlithium cell or energy source. Battery vol-tage must be held between 2.5 and 3.4 volts

for proper operation. A maximum load of .5A at 25C in the absence of VCC powershould be used to size the external energysource.

SQW (Square Wave Output) The SQWpin can output a signal from one of 13 tapsprovided by the internal divider stages of theReal Time Clock. The frequency of the SQWpin can be changed by programmingRegister A as shown in Table 1. The SQWsignal can be turned on and off using theSQWE bit in Register B. The SQW signal isnot available when V

CCis less than 4.25

volts typical.

TABLE 1: PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY

SELECT BITS REGISTER A tPI PERIODIC SQW OUTPUT

RS3 RS2 RS1 RS0 INTERRUPT RATE FREQUENCY

0 0 0 0 None None

0 0 0 1 3.90625 ms 256 Hz

0 0 1 0 7.8125 ms 128 Hz0 0 1 1 122.070 s 8.192 kHz

0 1 0 0 244.141 s 4.096 kHz

0 1 0 1 488.281 s 2.048 kHz

0 1 1 0 976.5625 s 1.024 kHz

0 1 1 1 1.953125 ms 512 Hz

1 0 0 0 3.90625 ms 256 Hz

1 0 0 1 7.8125 ms 128 Hz

1 0 1 0 15.625 ms 64 Hz

1 0 1 1 31.25 ms 32 Hz

1 1 0 0 62.5 ms 16 Hz

1 1 0 1 125 ms 8 Hz

1 1 1 0 250 ms 4 Hz

1 1 1 1 500 ms 2 Hz


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X1, X2 These pins connect to a standard32.768 kHz quartz crystal. The internal os-cillator circuitry is designed for operation witha crystal having a specified load capa-citance (CL) of 6 pF. Each of the pins (X1

and X2) require the installation of an ex-ternal 10 pF capacitor.

RCLR# The RCLR# pin is used to clear(set to logic 1) all 114 bytes of general pur-pose RAM but does not affect the RAM as-sociated with the real time clock. In order toclear the RAM, RCLR# must be forced to aninput logic of 0 (-0.3 to +0.8 volts) duringbattery back-up mode when VCC is not ap-plied. The RCLR# function is designed to beused via human interface (shorting to groundmanually or by switch) and not to be drivenwith external buffers. This pin is internally

pulled up.

AD0-AD7 (Multiplexed Bidirectional

Address/Data Bus) Multiplexed busessave pins because address information anddata information time share the same signalpaths. The addresses are present during thefirst portion of the bus cycle and the samepins and cycle paths are used for data in thesecond portion of the cycle. Address/datamultiplexing does not slow the access timeof the VT82885 since the bus change fromaddress to data occurs during the internalRAM access time. Addresses must be validprior to the falling edge of AS, at which timethe VT82885 latches the address from AD0to AD6. Valid data must be present and heldstable during the latter portion of the RD# orWR# pulses. In a read cycle the VT82885outputs 8 bits of data during the latter portionof the RD# or RD# pulses. The read cycle isterminated and the bus returns to a highimpedence state as RD# transistions high asin Intel timing.

AS (Adress Strobe Input) A positivegoing address strobe pulse serves to

demultiplex the bus. The falling edge of AScauses the address to be latched within theVT82885.

RD# (Read Strobe) The RD# pin identifiesthe time period when the VT82885 drives thebus with read data. The RD# signal is thesame definition as the Output Enable (OE#)signal on a typical memory.

WR# (Write Strobe) The WR# pin is usedto indicate a write cycle.

CS# (Chip Select Input) The Chip Selectsignal must be asserted low for a bus cyclein the VT82885 to be accessed. CS# must

be kept in the active state during RD# andWR#. Bus cycles which take place withoutasserting CS# will latch addresses but noaccess will occur. When VCC is below 4.25volts, the VT82885 internally inhibits accesscycles by internally disabling the CS# input.This action protects both the real time clockdata and RAM data during power outages.

IRQ# (Interrupt Request Output) TheIRQ# pin is an active low output of theVT82885 that can be used as an interruptinput to a processor. The IRQ# outputremains low as long as the status bit causingthe interrupt is present and thecorresponding interrupt-enable bit is set. Toclear the IRQ# pin the processor programnormally reads the C register. The RESET#pin also clears pending interrupts.

When no interrupt condition is present, theIRQ# level is in the high impedence state.Multiple interrupting devices can beconnected to an IRQ# bus. The IRQ# bus isan open drain output and requires anexternal pull-up resistor.

RESET# (Reset Input) The RESET# pin

has no effect on the clock, calendar, orRAM. On power-up the RESET# pin can beheld low for a time in order to allow thepower supply to stabilize. The amount oftime that RESET# is held low is dependenton the application. However, if RESET# isused on power-up, the time RESET# is lowshould exceed 200 ms to make sure that theinternal timer that controls the VT82885 onpower-up has timed out. When RESET# islow and VCC is above 4.25 volts, thefollowing occurs:

A. Periodic Interrupt Enable (PEI) bit is

cleared to zero.

B. Alarm Interrupt Flag (AIE) bit is clearedto zero.

C. Update Ended Interrupt Flag (UF) bit iscleared to zero.

D. Interrupt Request Status Flag (IRQF) bitis cleared to zero.


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E. Periodic Interrupt Flag (PF) bit is clearedto zero.

F. The device is not accessible untilRESET# is returned high.

G. Alarm Interrupt Flag (AF) bit is cleared tozero.

H. IRQ# pin is in the high impedence state.

I. Square Wave Output Enable (SQWE)bit is cleared to zero.

J. Update Ended Interrupt Enable (UIE) iscleared to zero.

In a typical application RESET# can beconnected to VCC. This connection will allowthe VT82885 to go in and out of power failwithout affecting any of the control registers.

ADDRESS MAP

The address map of the VT82885 is shownin Figure 2. The address map consists of114 bytes of user RAM, 10 bytes of RAMthat contain the RTC time, calendar and

alarm data, and four bytes which are usedfor control and status. All 128 bytes can bedirectly written or read except the following:

1. Registers C and D are read-only.

2. Bit 7 of Register A is read-only.

3. The high order bit of the seconds byte isread-only.

The contents of four registers (A, B, C andD) are described in the Register section.

FIGURE 2: ADDRESS MAP VT82885

TIME, CALENDAR AND ALARMLOCATIONS

The time and calendar information isobtained by reading the appropriate memorybytes. The time, calendar and alarm are set

or initialized by writing the appropriate RAMbytes. The contents of the ten time, calen-dar and alarm bytes can be either Binary orBinary-Coded Decimal (BCD) format. Be-fore writing the internal time, calendar andalarm registers, the SET bit in Register B

0 SECONDS 00

1 SECONDS ALARM 01

2 MINUTES 02

3 MINUTES ALARM 03

4 HOURS 04

5 HOURS ALARM 05

6 DAY OF THE WEEK 06

7 DAY OF THE MONTH 07

8 MONTH 08

9 YEAR 09

10 REGISTER A 0A

11 REGISTER B 0B

12 REGISTER C 0C

13 REGISTER D 0D127

0 00

OD

0E

13

14

7F

14 Bytes

Clock and Control

Status Registers

114 BytesStorage

Registers

Binary or BCD Input


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should be written to a logic one to preventupdates from occurring while access is be-ing attempted. In addition to writing the tentime, calendar and alarm registers in a se-lected format (binary or BCD), the data

mode bit (DM) of Register B must be set tothe appropriate logic level. All ten time, cal-endar and alarm bytes must use the samedata mode. The set bit in Register B shouldbe cleared after the data mode bit has beenwritten to allow the real time clock to updatethe time and calendar bytes. Once initial-ized, the real time clock makes all updates inthe selected mode. The data mode can-notbe changed without reinitializing the ten databytes. Table 2 shows the binary and BCDformats of the ten time, calendar and alarmlocations. The 24-12 bit cannot be changedwithout reinitializing the hour loca-tions.

When the 12-hour format is selected, thehigh order bit of the hours byte repre-sentsPM when it is a logic one. Once per secondthe ten bytes are advanced by one secondand checked for an alarm condition. If a readof the time and calendar data oc-curs during

an update, a problem exists where seconds,minutes, hours, etc. may not correlate. Theprobability of reading in-correct time andcalendar data is low. Sev-eral methods ofavoiding any possible incor-rect time and

calendar reads are covered later in this text.The three alarm bytes can be used in twoways. First, when the alarm time is written inthe appropriate hours, minutes and secondsalarm locations, the alarm interrupt is initi-ated at the specified time each day if thealarm enable bit is high. The second usecondition is to insert a dont care state inone or more of the three alarm bytes. Thedont care code is any hexadecimal valuefrom C0 to FF. The two most significant bitsof each byte set the dont care conditionwhen at logic 1. An alarm will be generated

each hour when the dont care bits are setin the hours byte. Similarily, an alarm isgenerated every minute with dont carecodes in the hours and minute alarm bytes.The dont care codes in all three alarmbytes create an interrupt every second.

TABLE 2: TIME. CALENDAR AND ALARM DATA MODES

ADDRESS DECIMAL RANGE

LOCATION FUNCTION RANGE BINARY DATA MODE BCD DATA MODE

0 Seconds 0-59 00-3B 00-59

1 Seconds Alarm 0-59 00-3B 00-59

2 Minutes 0-59 00-3B 00-59

3 Minutes Alarm 0-59 00-3B 00-59

4 Hours-12-hr Mode 1.12 01-0C AM, 81-8C PM 01-12AM,81-92PM

Hours-24-hr Mode 0-23 00-17 00-23

5 Hours Alarm-12-hr 1-12 01-0C AM, 81-8C PM 01-12AM,81-92PM

Hours Alarm-24-hr 0-23 00-17 00-23

6 Day of the WeekSunday = 1

1-7 01-07 01-07

7 Date of the Month 1-31 01-1F 01-31

8 Month 1-12 01-0C 01-12

9 Year 0-99 00-63 00-99

NONVOLATILE RAM


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The 114 general purpose nonvolatile RAMbytes are not dedicated to any special func-tion within the VT82885. They can be usedby the processor program as nonvolatilememory and are fully available during the

update cycles.INTERRUPTS

The RTC plus RAM includes three separate,fully automatic sources of interrupt for a pro-cessor. The alarm interrupt can be pro-grammed to occur at rates from once persecond to once per day. The peridoic inter-rupt can be selected for rates from 500 ms

to 122 s. The update-ended interrupt canbe used to indicate to the program that anupdate cycle is complete. Each of theseindependent interrupt conditions is de-scribed in greater detail in other sections of

this text.

The processor program can select whichinterrupts, if any, are going to be used.Three bits in Register B enable the inter-rupts. Writing a logic 1 to an interrupt-enablebit permits that interrupt to be initi-ated whenthe event occurs. A zero in an interrupt-enable bit prohibits the IRQ# pin from beingasserted from the interrupt condition. If aninterrupt flag is already set when theinterrupt is enabled, IRQ# is im-mediatelyset at an active level, although the interruptinitiating the event may have occurred muchearlier. As a result, there are cases wherethe program should clear such earlierinitiated interrupts before first ena-bling newinterrupts.

When an interrupt event occurs, the relatingflag bit is set to logic 1 in Register C. Theseflag bits are set independent of the state ofthe corresponding enable bit in Register B.The flag bit can be used in a polling modewithout enabling the corresponding enablebits. The interrupt flag bit is a status bitwhich software can interrogate as neces-sary. When the flag is set, an indication isgiven to software that an interrupt event hasoccurred since the flag bit was last read.;however, care should be taken when usingthe flag bits as they are cleared each timeRegister C is read. Double latching is in-cluded with Register C so that bits which areset remain stable throughout the read cycle.All bits which are set (high) are cleared whenread and new interrupts which are pending

during the read cycle are held until after thecycle is completed. One, two, or three bitscan be set when reading Register C. Eachutilized flag bit should be examined whenread to ensure that no interrupts are lost.

The second flag bit usage method is withfully enabled interrupts. When an interruptflag bit is set and the corresponding inter-rupt enable bit is also set, the IRQ# pin isasserted low. IRQ# is asserted as long as atleast one of three interrupt sources has itsflag and enable bits both set. The IRQF bit inRegister C is a one whenever the IRQ# pinis being driven low. Determination that theRTC initiated an interrupt is accom-plishedby reading Register C. A logic one in bit 7(IRQF bit) indicates that one or moreinterrupts have been initiated by the

VT82885. The act of reading Register Cclears all active flag bits and the IRQF bit.

OSCILLATOR CONTROL BITS

The VT82885s internal oscillator can beturned on and off as required. A pattern of010 in bits 4 through 6 of Register A will turnthe oscillator on and enable the countdownchain. A pattern of 11X will turn the oscilla-tor on, but holds the countdown chain of theoscillator in reset. All other combinations ofbits 4 through 6 keep the oscillator off.

SQUARE WAVE OUTPUT SELECTION

Thirteen of the 15 divider taps are madeavailable to a 1-of-15 selector, as shown inthe block diagram of Figure 1. The firstpurpose of selecting a divider tap is togenerate a square wave output signal on theSQW pin. The PS0-RS3 bits in Register Aestablish the square wave output frequency.These frequencies are listed in Table 1. TheSQW frequency selection shares its 1-of-15selector with the periodic interrupt genera-tor. Once the frequency is selected, theoutput of the SQW pin can be turned on andoff under program control with the square

wave enable bit (SQWE)

PERIODIC INTERRUPT SELECTION

The periodic interrupt will cause the IRQ#pin to go to an active state from once every

500 ms to once every 122 s. This functionis separate from the alarm interrupt whichcan be output from once per second to onceper day. The periodic interrupt rate is se-


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lected using the same Register A bits whichselected the square wave frequency (seeTable 1). Changing the Register A bits af-fects both the square wave frequency andthe periodic interrupt output. However, each

function has a separate enable bit in Regis-ter B. The SQWE bit controls the squarewave output. Similarly the periodic interruptis enabled by the PIE bit in Register B. Theperiodic interrupt can be used with softwarecounters to measure inputs, create outputintervals, or await the next needed softwarefunction.

UPDATE CYCLE

The VT82885 executes an update cycleonce per second regardless of the SET bit inRegister B. When the SET bit in Register Bis set to one, the user copy of the double

buffered time, calendar and alarm bytes isfrozen and will not update as the time in-crements. However, the time countdownchain continues to update the internal copyof the buffer. This feature allows time tomaintain accuracy independent of reading orwriting the time, calendar and alarm buf-fersand also guarantees that time and cal-endarinformation is consistent. The update cyclealso compares each alarm byte with thecorresponding time byte and issues analarm if a match or if a dont care code ispresent in all three positions.

There are three methods that can handleaccess of the real time clock that avoid any

possibility of accessing inconsistent time andcalendar data. The first method uses theupdate-ended interrupt. If enabled, aninterrupt occurs after every up date cyclethat indicates that over 999 ms are available

to read valid time and date information. Ifthis interrupt is used, the IRQF bit in Regis-ter C should be cleared before leaving theinterrupt routine.

A second method uses the update-in-progress bit (UIP) in Register A to determineif the update cycle is in progress. The UIP bitwill pulse once per second. After the UIP bit

goes high, the update transfer occurs 244 slater. If a low is read on the UIP bit, the user

has at least 244 sbefore the time/calendardata will be changed. There-fore, the usershould avoid interrupt service routines that

would cause the time needed to read validtime/calendar data to exceed 244 s.

The third method uses a periodic interrupt todetermine if an update cycle is in progress.The UIP bit in Register A is set high be-tween the setting of the PF bit in Register C(see Figure3). Periodic interrupts that occurat a rate of greater than tBUC allow valid timeand date information to be reached at eachoccurrence of the periodic interrupt. Thereads should be complete within 1 (tP1/2 +tBUC) to ensure that data is not read duringthe update cycle.

FIGURE 3: UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP

UIP

UF

PF

(tPI)/2 tBUC

1 sec

(tPI)/2 tPI

tUC

REGISTERS

The VT82885 has four control registerswhich are accessible at all times, even dur-ing the update cycle.

REGISTER A


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MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

UIP

The Update in Progress (UIP) bit is a statusflag that can be monitored. When the UIP bitis one, the update transfer will soon oc-cur.When UIP is a zero, the update transfer will

not occur for at least 244 s. The time,calendar and alarm information in RAM isfully available for access when the UIP bit iszero. The UIP bit is read only and is not af-fected by RESET#. Writing the SET bit inRegister B to a one inhibits any updatetransfer and clears the UIP status bit.

DV0, DV1, DV2

These three bits are used to turn the oscilla-tor on or off and to reset the countdownchain. A pattern of 010 is the only combina-tion of bits that will turn the oscillator on andallow the RTC to keep time. A pattern of 11Xwill enable the oscillator but holds thecountdown chain in reset. The next updatewill occur at 500 ms after a pattern of 010 iswritten to DV0, DV1 and DV2.

RS3, RS2 RS1, RS0

These four rate-selection bits select one ofthe 13 taps on the 15-stage divider or dis-

able the divider output. The tap selected canbe used to generate an output square wave(SQW pin) and/or a periodic interrupt. Theuser can do one of the following:

1. Enable the interrupt with the PIE bit;

2. Enable the SQW output pin with theSQWE bit;

3. Enable both at the same time and thesame rate;

4. Enable neither.

Table 1 lists the periodic interrupt rates andthe square wave frequencies that can bechosen with the RS# bits. These fourread/write bits are not affected by RESET#.

REGISTER B

MSB LSB


SET PIE AIE UIE SQWE DM 24/12 DSE

SET

When the SET bit is a zero, the updatetransfer functions normally by advancing thecounts once per second. When the SET bitis written to a one, any update transfer is

inhibited and the program can initialize thetime and calendar bytes without an updateoccurring in the midst of initializing. SET is aread/write bit that is not modified by RE-SET# or internal functions of the VT82885.

PIE

The periodic interrupt enable PIE bit is aread/write bit which allows the Periodic In-terrupt Flag (PF) bit in Register C to drivethe IRQ# pin low. When the PIE bit is set toone, periodic interrupts are generated bydriving the IRQ# pin low at a rate specified

by the RS3-RS0 bits of Register A. A zero inthe PIE bit blocks the IRQ# output from be-ing driven by a periodic interrupt, but thePeriodic Flag (PF) bit is still set at the peri-odic rate. PIE is not modified by any internalVT82885 functions, but is cleared to zero onRESET#.

AIE

The Alarm Interrupt Enable (AIE) bit is aread/write bit which, when set to one, per-mits the Alarm Flag (AF) bit in Register C toassert IRQ#. An alarm interrupt occurs foreach second that the three time bytes equalthe three alarm bytes including a dont carealarm code of binary 11XXXXXX. When theAIE bit is set to zero, the AF bit does notiniate the IRQ# signal. The RE-SET# pinclears AIE to zero. The internal functions ofthe VT82885 do not affect the AIE bit.

UIE

The Update Ended Interrupt Enable (UIE) bitis a read/write that enables the Update EndFlag (UF) bit in Register C to assert IRQ#.The RESET# pin going low or the SET bitgoing high clears to UIE bit.

SQWE

When the Square Wave Enable (SQWE) bitis set to a one, a square wave signal at thefrequency set by the rate-selection bits RS3through RS0 is driven out on a SQW pin.When the SQWE bit is set to zero, the SQWpin is held low; the state of SQWE is cleared


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by the RESET# pin. SQWE is a read/writebit.

DM

The Data Mode (DM) bit indicates whether

time and calendar information is in binary orBCD format. The DM bit is set by theprogram to the appropriate format and canbe read as required. This bit is not modifiedby internal functions or RESET#. A one inDM signifies binary data while a zero in DMspecifies Bnary Coded Decimal (BCD) data.

24/12

The 24/12 control bit establishes the formatof the hours byte. A one indicates the 24-hour mode and a zero indicates the 12-hourmode. This bit is read/write and is notaffected by internal functions of RESET#.

DSE

The Daylight Savings Enable (DSE) bit is aread/write bit which enables two specialupdates when DSE is set to one. On the firstSunday in April the time increments from1:59:59 AM to 3:00:00 AM. On the lastSunday in October when the time reaches1:59:59 AM it changes to 1:00:00 AM. Thesespecial updates do not occur when the DSEbit is a zero. This bit is not affected byinternal functions or RESET#.

REGISTER CMSB LSB


IRQF PF AF UF 0 0 0 0

IRQF

The interrupt Request Flag (IRQF) bit is setto a one when one or more of the followingare true:

PF = PIE = 1AF = AIE = 1

UF = UIE = 1That is, IRQF = PF PIE + AF AIE + UF UIE.

Any time the IRQF bit is one, the IRQ# pin isdriven low. All flag bits are cleared afterRegister C is read by the program or whenthe RESET# pin is low.

PF

The Periodic Interrupt Flag (PF) is a read-only bit whcih is set to a one when an edgeis detected on the selected tap of the dividerchain. The RS3 through RS0 bits establish

the periodic rate. PF is set to a oneindependent of the state of the PIE bit.When both PF and PIE are ones, the IRQ#signal is active and will set the IRQF bit. ThePF bit is cleared by a RESET# or a softwareread of Register C.

AF

A one in the Alarm Interrupt Flag (AF) bitindicates that the current time has matchedthe alarm time. If the AIE bit is also a one,the IRQ# pin will go low and a one willappear in the IRQF pin. UF is cleared by

reading Register C or a RESET#.UF

The Update Ended Interrupt Flag (UF) bit isset after each update cycle. When the UIEbit is set to one, the one in UF causes theIRQF bit to be a one which will assert theIRQ# pin. UF is cleared by reading RegisterC or a RESET#.

BIT 0 THROUGH BIT 3

These are unused bits of the status RegisterC. These bits always read zero and cannot

be written.REGISTER D

MSB LSB


VRT 0 0 0 0 0 0 0

VRT

This bit is not writeable and should alwaysbe one when read. If a zero is ever present,an exhausted external lithium energy sourceis indicated and both the contents of the

RTC data and RAM data are questionable.This bit is unaffected by RESET#.

BIT 6 THROUGH BIT 0

The remaining bits of Register D are notusable. They cannot be written and, whenread, they will always read zero.

ABSOLUTE MAXIMUM RATINGS*


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VT82885


VOLTAGE ON ANY PIN RELATIVE TO GROUND -0.3V TO +7.0V

OPERATING TEMPERATURE 0C TO 70C

STORAGE TEMPERATURE -40C TO +70C

SOLDERING TEMPERATURE 260C FOR 10 SECONDS

*This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure toabsolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0C TO 70C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Voltage VCC 4.5 5.0 5.5 V 1

Input Logic 1 VIH 2.2 VCC+0.3 V 1

Input Logic 0 VIL -0.3 +0.8 V 1

DC ELECTRICAL CHARACTERISTICS (0C TO 70C, VCC = 4.5 TO 5.5V)


Power Supply Current ICC1 5 10 mA 2

Input Leakage IIL -1.0 +1.0 A 3

I/O Leakage ILO -1.0 +1.0 A 4

Input Current IMOT -1.0 +500 A 3

Output @ 2.4V IOH -1.0 mA 1,5

Output @ 0.4V IOL 4.0 mA 1

Write Protect Voltage VTP 4.0 4.25 4.5 V

CAPACITANCE (tA = 25C)


Input Capacitance CIN 5 pF

Output Capacitance COUT 7 pF

AC ELECTRICAL CHARACTERISTICS (0C TO 70C, VCC = 4.5V TO 5.5V)


Cycle Time tCYC 385 DC ns

Pulse Width, DS/E Low orRD/WR# High

PWEL 150 ns


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Pulse Width, DS/E High orRD/WR# Low

PWEH 125 ns

Input Rise and Fall Time tR, tF 30 ns

R/W# Hold Time tRWH 10 ns

R/W# Setup Timebefore DS/E

tRWS 50 ns

Chip Select Setup Timebefore DS, WR#, or RD#

tCS 20 ns

Chip Select Hold Time tCH 0 ns

Read Data Hold Time tDHR 10 80 ns

Write Data Hold Time tDHW 0

Muxed Address Valid Timeto AS/ALE Fall

tASL 30 ns

Muxed Address Hold Time tAHL 10 nsDelay Time DS/Eto AS/ALE Rise

tASD 25 ns

Pulse Width AS/ALE High PWASH 60 ns

Delay Time, AS/alEto DS/E Rise

tASED 40 ns

Output Data Delay Timefrom DS/E or RD#

tDDR 20 120 ns

DataSetup Time tDSW 100 ns

Reset Pulse Width tRWL 5 s

IRQ# Release from DS tIRDS 2 s

IRQ# Release fromRESET#

tIRR 2 s

Delay Time before UpdateCycle

tBUC 244 s

Periodic Interrupt TimeInterval

tPI See Table1

Time of Update Cycle tUC 1708 s

NOTES

1. All voltages are referenced to ground.

2. All outputs are open.

3. Applies to the AD0-AD7 pins, the IRQ#

pin and the SQW pin when each is in thehigh impedence state.

4. The IRQ# pin is open drain.

5. Measured with a load as shown inFigure 4.

FIGURE 4: OUTPUT LOAD


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D.U.T.

+5 VOLTS

1.1 K

50 pF680

VT82885 BUS TIMING FOR WRITE CYCLE


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AS

RD#

WR#

CS#

AD0-AD7

PWEL

tASD

tASD

PWASH

tCYC

tCS

tASED

PWEH

tDSW

tAHL

tASL

tCH

tDHW

VT82885 BUS TIMING FOR READ CYCLE


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AS

RD#

WR#

CS#

AD0-AD7

PWEL

tASD

tASD

PWASH

tCYC

tCS

tASED

PWEH

tDDR

tAHL

tASL tDHR

tCH

VT82885 IRQ RELEASE DELAY TIMING

RD#

RESET#

IRQ#

tRDS tIRR

tRWL

POWER DOWN/POWER UP TIMING


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CURRENT SUPPLIEDFROM EXTERNALLITHIUM ENERGY CELL

tR

CS#

tF

VBAT

4.5V

VCC

tREC

DATA RETENTIONtDR

tPD

POWER DOWN/POWER UP TIMING


CS# at VIH before Power-Down tPD 0 s

VCC slew from 4.5V to 0V(CS# at VIH)

tF 300 s

VCC slew from 0V to 4.5V(CS# at VIH)

tR 100 s

CS# at VIH after Power-Up tREC 20 200 ms

(tA = 25C)


Expected Data Retention tDR 10 years

NOTE

The real time clock will keep time to an

accuracy of 1 minute per month during dataretention time for the period of tDR.

WARNING

Under no circumstances are negativeundershots, of any amplitude, allowed whendevice is in battery backup mode.

Vt82885 Rolando

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