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Com put er Organizat ionTC 1016
Edgar Berm ejo
Chapt er 4
Mem ory syst em s: Organizat ionand a rc h it ec t u re
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Chapt er 4Mem ory syst em s: Organizat ion and
arch i t ec tu re
4.1 Int roduc t ion
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Charac ter is t i csLocat ion Per f o r m an ce
Internal (e.g. processor registers,main memory, cache)
Access time
External (e.g. optical disks,magnetic disks, tapes)
Cycle time
Capaci ty Transfer rate
Number of words Ph y s ica l Ty p e
Number of bytes Semiconductor
Un i t o f Tr a n sf er Magnetic
Word Optical
Block Magneto-optical
Access Met h od Ph y sica l Ch ar act er i st ics
Sequential Volatile/nonvolatile
Direct Erasable/nonerasable
Random OrganizationAssociative Memory modules
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Loca t ion
CPU
Internal
External
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Capac i ty
Word size
The natural unit of organisation
Number of words
or Bytes
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Uni t o f Transfer Internal
Usually governed by data bus width
External
Usually a block which is much larger than a
word
Addressable unit
Smallest location which can be uniquelyaddressed
Word internally
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Ac c ess Met hods (1) Sequential
Start at the beginning and read through in order(Access must be made in a specific linearsequence)
Access time depends on location of data andprevious location
e.g. tape Direct
Individual blocks have unique address
Access is by jumping to vicinity plus sequentialsearch
Access time depends on location and previouslocation
e.g. disk
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Ac c ess Met hods (2)
Random
Individual addresses identify locations exactly
Access time is independent of location orprevious access
e.g. RAM
Associative
Data is located by a comparison with contents
of a portion of the storeAccess time is independent of location or
previous access
e.g. cache
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From a user s po in t o f v iew
The two most important characteristics ofmemory are:
CapacityPerformance
PerformanceAccess time (latency)
Memory cycle time
Transfer rate
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Memory Per formanc e
Access time (latency)
For random-access memory, the time from the
instant that an address is presented to thememory to the instant that data have beenstored or made available for use.
For non-random-access memory, access time
is the time it takes to position the readwritemechanism at the desired location.
Memory cycle time
This concept is primarily applied to random-access memory and consists of the accesstime plus any additional time required before asecond access can commence.
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Mem ory Hierarc hy
How much? How fast? How expensive?
Faster access time, greater cost per bit Greater capacity, smaller cost per bit
Greater capacity, slower access time
Not to rely on a single memory
component or technology, but to employ am em o r y h i er a r ch y
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Mem ory Hierarc hy
As one goes down the hierarchy, thefollowing occur:
a. Decreasing cost per bit
b . Increasing capacity
c. Increasing access time
d . Decreasing frequency of access of thememory by the processor
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Mem ory Hierarc hy
Registers
In CPU
Internal or Main memory
May include one or more levels of cache
RAM
External memory
Backing store
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Memory H ierarc hy - Diagram
Sm aller, m ore expensive, faster m emories
are supplemented by larger, cheaper,slower memories.
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Per formance
Access time
Time between presenting the address and
getting the valid data
Memory Cycle time
Time may be required for the memory torecover before next access
Cycle time is access + recovery
Transfer Rate
Rate at which data can be moved
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Physic a l Types
Semiconductor
RAM
Magnetic
Disk & Tape
Optical
CD & DVD & BD
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Phys ic a l Charac t er is t ic s
Decay
Volatility
Erasable
Power consumption
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Hierarc hy L is t
Registers
L1 Cache
L2 Cache L3 Cache
Main memory
Disk cache
Disk
Optical Tape
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Chapt er 4Mem ory syst em s: Organizat ion and
arch i t ec tu re
4.2 Cac he
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Cache
Small amount of fast memory
Sits between normal main memory and
CPU May be located on CPU chip or module
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Cache
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Cac he operat ion overv iew
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast) If not present, read required block from
main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify whichblock of main memory is in each cache
slot
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Cac he/Main Mem ory St ruc t ure
On the majority of current CPUs thememory cache is organized in 64-byte
lines. 512 KB L2 memory cache is divided into
8,192 lines
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Cac he/Main Mem ory St ruc t ure
Direct mapping
Is the simplest way of creating a memorycache
Main RAM memory is divided into the samenumber of lines there are inside the memorycache
1 GB of RAM will be divided into 8,192 blockseach one with 128 KB
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Cac he/Main Mem ory St ruc t ure
When the CPU asks for a given address from theRAM memory (e.g., address 1,000), the cache
controller will load a line (64 bytes) from theRAM memory and store this line on the memorycache (i.e., addresses 1,000 through 1,063)
So if the CPU asks again the contents of thisaddress or of the next few addresses right afterthis address (i.e., any address from 1,000 to
1,063) they will be already inside the cache.
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Cac he/Main Mem ory St ruc t ure
Fully associative
There is no hard linking between the lines ofthe memory cache and the RAM memorylocations.
The cache controller can store any address
This configuration is the most efficient one
The control circuit is far more complex, as itneeds to keep track of what memory locationsare loaded inside the memory cache
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Set 1
Set 2
Set 2048
Block 1
Block 2
Block 2048
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Cac he/Main Mem ory St ruc t ure
The mapping is very similar to whathappens with the direct mapped cache
The difference is that for each memoryblock there is now more than one line
available on the memory cache
Each line can hold the contents from any
address inside the mapped block
Wh t h i f h b i
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What happens i f w e have a b iggerm emory cac he?
Increasing the memory cache isnt somethingthat guarantees increase in performance.
Increasing the size of the memory cache assures
that more data will be cached, but the questionis whether the CPU is using this extra data ornot.
For example, suppose a single-core CPU with 4MB L2 cache. If the CPU is using heavily 1 MBbut not so heavily the other 3 MB (i.e., the mostaccessed instructions are taking up 1 MB and on
the other 3 MB the CPU cached instructions arenot being called so much), chance is that thisCPU will have a similar performance of anidentical CPU but with 2 MB or even 1 MB L2
cache
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Typic a l Cac he Organizat ion
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In t e l Cac he Evolut ion
Problem SolutionProcessor on whichfeature first appears
External memory slower than the system bus. Add external cache using faster
memory technology.
386
Increased processor speed results in external busbecoming a bottleneck for cache access.
Move external cache on-chip,operating at the same speed as the
processor.
486
Internal cache is rather small, due to limited space on
chipAdd external L2 cache using faster
technology than main memory
486
Contention occurs when both the Instruction Prefetcher
and the Execution Unit simultaneously require access to
the cache. In that case, the Prefetcher is stalled while the
Execution Units data access takes place.
Create separate data andinstruction caches.
Pentium
Increased processor speed results in external busbecoming a bottleneck for L2 cache access.
Create separate back-side bus that
runs at higher speed than the main
(front-side) external bus. The BSBis dedicated to the L2 cache.
Pentium Pro
Move L2 cache on to the
processor chip.
Pentium II
Some applications deal with massive databases and must
have rapid access to large amounts of data. The on-chip
caches are too small.
Add external L3 cache. Pentium III
Move L3 cache on-chip. Pentium 4
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Chapt er 4Mem ory syst em s: Organizat ion andarch i t ec tu re
4.3 In terna l m em ory
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Mem ory Cel l Operat ion
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Sem ic onduc t or Memory Types
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St at ic RAM
Bits stored as on/off switches
No charges to leak
No refreshing needed when powered More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
Uses flip-flops
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SRAM v DRAM
Both volatile
Power needed to preserve data
Dynamic cellSimpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
StaticFaster
Cache
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Read Only Mem ory (ROM)
Permanent storage
Nonvolatile
Microprogramming Library subroutines
Systems programs (BIOS)
Function tables
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Refreshing
Refresh circuit included on chip
Read & Write back
Takes time
Slows down apparent performance
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Error Correc t ion
Hard Failure
Permanent defect
Soft Error
Random, non-destructive
No permanent damage to memory
Detected using Hamming error correcting
code
E C i C d F i
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Error Correc t ing Code Func t ion
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Error Correc t ion
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Error Correc t ion
Error Correc t ion
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Error Correc t ion
Advanc ed DRAM Organizat ion
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Advanc ed DRAM Organizat ion
Basic DRAM same since first RAM chips
Enhanced DRAMContains small SRAM as well
SRAM holds last line read (c.f. Cache!)
Cache DRAM
Larger SRAM component
Use as cache
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Vi rt ua l m em ory
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Vi rt ua l m em ory
The area of the hard disk that stores theRAM image is called a page f i l e.
It holds pages of RAM on the hard disk, andthe operating system moves data back andforth between the page file and RAM.
On a Windows machine, page files have a.SWP extension.
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Chapt er 4Mem ory syst em s: Organizat ion andarch i t ec tu re
4.3 Ex t ernal m em ory
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Magnet ic Disk
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g
Disk substrate coated with magnetizablematerial (iron oxiderust)
Substrate used to be aluminium
Now glass
Improved surface uniformity
Increases reliability
Reduction in surface defects
Reduced read/write errors
Lower flight heights (See later)
Better stiffness
Better shock/damage resistance
Read and Wr i t e Mec hanism s
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Recording & retrieval via conductive coil called a head
May be single read/write head or separate ones
During read/write, head is stationary, platter rotates
Write Current through coil produces magnetic field
Pulses sent to head
Magnetic pattern recorded on surface below
Read (traditional)
Magnetic field moving relative to coil produces current
Coil is the same for read and write
Read (contemporary)
Separate read head, close to write head
Partially shielded magneto resistive (MR) sensor
Electrical resistance depends on direction of magnetic field
High frequency operation
Higher storage density and speed
Induc t ive Wr i t e MR Read
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Dat a Organizat ion and Form at t ing
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Concentric rings or tracks
Gaps between tracks
Reduce gap to increase capacity
Same number of bits per track (variablepacking density)
Constant angular velocity
Tracks divided into sectors
Minimum block size is one sector
May have more than one sector per block
Disk Dat a Layout
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Disk Ve loc i t y
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Bit near centre of rotating disk passes fixed pointslower than bit on outside of disk
Increase spacing between bits in different tracks
Rotate disk at constant angular velocity (CAV)Gives pie shaped sectors and concentric tracks
Individual tracks and sectors addressable
Move head to given track and wait for given sector
Waste of space on outer tracks
Lower data density
Can use zones to increase capacity
Each zone has fixed bits per trackMore complex circuitry
Disk Layout Met hods Diagram
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Finding Sec t ors
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Must be able to identify start of track andsector
Format disk
Additional information not available to userMarks tracks and sectors
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Charac ter is t i cs
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Fix ed/Movable Head Disk
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Fixed head
One read/write head per track
Heads mounted on fixed ridged arm
Movable headOne read/write head per side
Mounted on a movable arm
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Mul t ip le Pla t t ers
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Floppy Disk
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8, 5.25, 3.5
Small capacity
Up to 1.44Mbyte (2.88M never popular)
Slow
Universal
Cheap Obsolete?
Winc hest er Hard Disk (1)
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Developed by IBM in Winchester (USA)
Sealed unit
One or more platters (disks)
Heads fly on boundary layer of air as diskspins
Very small head to disk gap Getting more robust
Winc hest er Hard Disk (2)
U i l
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Universal
Cheap
Fastest external storage
Getting larger all the time
250 Gigabyte now easily available
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Typic a l Hard Disk Dr ive Param et ers
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RAID
R d d t A f I d d t Di k
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Redundant Array of Independent Disks
Redundant Array of Inexpensive Disks
6 levels in common use
Not a hierarchy
Set of physical disks viewed as singlelogical drive by O/S
Data distributed across physical drives
RAID 0
No redundancy
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No redundancy
Data striped across all disks
Round Robin striping
Increase speed
Multiple data requests probably not on samedisk
Disks seek in parallel
A set of data is likely to be striped acrossmultiple disks
RAID 1
Mirrored Disks
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Mirrored Disks
Data is striped across disks
2 copies of each stripe on separate disks
Read from either
Write to both
Recovery is simpleSwap faulty disk & re-mirror
No down time
Expensive
RAID 2
Disks are synchronized
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Disks are synchronized
Very small stripes
It stripes the bits across the disks
Error correction calculated acrosscorresponding bits on disks
Multiple parity disks store Hamming codeerror correction in corresponding positions
Lots of redundancy
ExpensiveNot used
RAID 3
Similar to RAID 2
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Similar to RAID 2
Only one redundant disk, no matter howlarge the array
Simple parity bit for each set ofcorresponding bytes
Data on failed drive can be reconstructedfrom surviving data and parity info
Very high transfer rates
RAID 4
Each disk operates independently
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Each disk operates independently
Good for high I/O request rate
Large stripes
Bit by bit parity calculated across stripeson each disk
Parity stored on parity disk
RAID 5
Like RAID 4
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Like RAID 4
Parity striped across all disks
Round robin allocation for parity stripe
Avoids RAID 4 bottleneck at parity disk
Commonly used in network servers
DOES NOT MEAN 5 DISKS!!!!!
RAID 6
Two parity calculations
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Two parity calculations
Stored in separate blocks on differentdisks
User requirement of N disks needs N+2
High data availability
Three disks need to fail for data loss
Significant write penalty
RAID 0, 1 , 2
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RAID 3 & 4
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RAID 5 & 6
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Dat a Mapping For RAID 0
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RAID
A disk array controller is a device which
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A disk array controller is a device whichmanages the physical disk drives andpresents them to the computer as logical
units. It almost always implements hardware
RAID, thus it is sometimes referred to as
RAID controller
Opt ic al St orage CD-ROM
Originally for audio
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O g a y o aud o
650Mbytes giving over 70 minutes audio
Polycarbonate coated with highlyreflective coat, usually aluminium
Data stored as pits
Read by reflecting laser
CD Operat ion
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Random Ac c ess on CD-ROM
Difficult
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Move head to rough position
Set correct speed
Read address
Adjust to required location
CD-ROM for & aga ins t
Large capacity (?)
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g p y ( )
Easy to mass produce
Removable
Robust
Expensive for small runs Slow
Read only
Ot her Opt ic a l St orage
CD-Recordable (CD-R)
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Now affordable
Compatible with CD-ROM drives
CD-RW
Erasable
Getting cheaper
Mostly CD-ROM drive compatible
Phase change
Material has two different reflectivities in differentphase states
Beam of laser light can change the material from onephase to the other
DVD - w hat s in a nam e?
Digital Video Disk
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Used to indicate a player for movies
Only plays video disks
Digital Versatile DiskUsed to indicate a computer drive
Will read computer disks and play video disks
Dogs Veritable Dinner Officially - nothing!!!
DVD - t echno logy
Multi-layer
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Very high capacity (4.7G per layer)
Full length movie on single disk
Using MPEG compression
Finally standardized
Movies carry regional coding Players only play correct region films
Can be fixed
DVD Wr i t ab le
Loads of trouble with standards
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First generation DVD drives may not readfirst generation DVD-W disks
First generation DVD drives may not readCD-RW disks
CD and DVD
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CD and DVD
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High-Def in it i on Opt i ca l Di sk s
To store high-definition videos and toprovide significantly greater storage
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provide significantly greater storagecapacity compared
Higher bit density is achieved by using alaser with a shorter wavelength
Blue-violet range
Data pits, which constitute the digital 1sand 0s, are smaller
Positions the data layer on the disk closer
to the laserEnables a tighter focus and less distortion and
thus smaller pits and tracks
High-Def in it i on Opt i ca l Di sk s
Blu-ray can store 25 GB on a single layerd l (BD ROM) d bl
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read only (BD-ROM), recordable once(BD-R), and rerecordable (BD-RE)
Magnet ic Tape
Serial accessIf the tape head is positioned at record 1 then
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If the tape head is positioned at record 1, thento read record N, it is necessary to read
physical records 1 through N 1, one at a timeIf the head is currently positioned beyond the
desired record, it is necessary to rewind thetape a certain distance and begin reading
forward
Slow
Very cheap
Backup and archive
Magnet ic Tape
7/31/2019 Tema 4 - Organizacin y arquitectura de sistemas de memoria
117/118
Magnet ic Tape
7/31/2019 Tema 4 - Organizacin y arquitectura de sistemas de memoria
118/118
LTO = Linear Tape-Open
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