Arquitectura de Computadoras - WordPress.com...Arquitectura de Computadoras Lenguaje Ensamblador J....
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Arquitectura de ComputadorasLenguaje Ensamblador
J. Irving [email protected]
Centro de Innovacion y Desarrollo Tecnologico en Computo
16 de marzo de 2016
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Table of contents
Introduccion
Componentes circuitales
Unidad Central de Procesamiento
MIPS instruction set
Representacion de Instrucciones
Logic Operations
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Introduccion
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Modelo de Bus
Figura : Modelo de Bus
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MemoriaI Arreglo de registros numerados
I Formatos de almacenamiento
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Memoria
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Unidad Central de Procesamiento
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Data path
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Fetch-execute cycle
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Unidad Central de Procesamiento
I Instruction Set. Coleccion de instrucciones que un procesadorpuede ejecutar.
I CompilacionI Lenguaje alto nivel (Compilacion)I Lenguaje ensamblador (Ensamble)I Codigo maquina
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Tipo de computadoras
I CISC - Complex Instruction SetComputers
MULT 2:3 5:2a = a * b
I RISC - Reduced Instruction SetComputers
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CISC vs RISC
I Perfomance equation
CISC RISC
Enfocada al harware Enfocada al Software
Carga y descarga de memo-ria incorporada en las in-trucciones
Carga y descarga son ins-trucciones separadas
Codigos cortos altos ciclospor segundo
Bajos ciclos por segundolargos codigos
Hardware para interpretar yguardar instrucciones
Harware necesario para losregistros
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MIPS Instruction set
I Microprocessor without Interlocked Pipeline Stages
I Basado en RISC
I Se utiliza en diversos sitemas embebidos: Windows Ce,Routers Cisco, Sony Play Station, Nintendo 64, PSP.
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Ejemplos
a = b + c
d = a− e
f = (g + h) + (i + j)
f = (g + h) − (i + j)
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Carga y Almacenamiento
I Load and Store
I Ejemplo:g = h + A[8];
I $s3 contiene la direccion base
I A[12] = A[10] + A[8];
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Carga y Almacenamiento
I Load and Store
I Ejemplo:g = h + A[8];
I $s3 contiene la direccion base
I A[12] = A[10] + A[8];
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Constantes
I Add inmediate
I Cero, registro $zero
I ¡Haz lo comun rapido!
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Representacion de Instrucciones
I ¿Como entiende la maquina las instrucciones?
I Ejemplo:
I Fields:
I Primero y ultimo indican la operacion
I Segundo indica el primer operando
I Tercero indica el segundo operando
I Cuarto indica el receptor
I Quinto opcional para la instruccion
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Representacion de Instrucciones
I ¿Como entiende la maquina las instrucciones?
I Ejemplo:
I Fields:
I Primero y ultimo indican la operacion
I Segundo indica el primer operando
I Tercero indica el segundo operando
I Cuarto indica el receptor
I Quinto opcional para la instruccion
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Instruction Format
I Instruction format. A form of representation of an instructioncomposed of fields of binary numbers.
I Machine language.Binary representation used forcommunication within a computer system.
I Machine code. Sequence of instructions in machine language.
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MIPS Instruction format
I op: Opcode: denotes the operation and format of aninstruction.
I rs: The fist register source operand.
I rt: The second register source operand.
I rd: Register destination operand.
I shamn: Shift amount.
I funct: Function code. Variant of the op field.
I ¿Limitaciones?
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MIPS Instruction format
I op: Opcode: denotes the operation and format of aninstruction.
I rs: The fist register source operand.
I rt: The second register source operand.
I rd: Register destination operand.
I shamn: Shift amount.
I funct: Function code. Variant of the op field.
I ¿Limitaciones?
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Instruction Format
I Register Type. R-type
I Inmediate type. I-type
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Instruction Format
Figura : MIPS instruction Encoding
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Assambly language translation
I Example
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Operaciones Logicas
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Making Decisions
I Conditional branches
I if statement with a go to statement
I Branch if equal
I Brach if not equal
I Jump
j L1 # go to label L
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Making Decisions
I Exercise
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If
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0,$s1,$s2
Exit:
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Loops
Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0,0($t1)
bne $t0, $s5, Exit
addi $s3, $s3 , 1
j Loop
Exit
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Procedures
I Procedure. A stored subroutine that performs a specific taskbased on the parameters with which it is provided.
I Steps:
1. Put parameters in a place where the procedure can accessthem.
2. Transfer control to the procedure.3. Acquire the storage resources needed for the procedure.4. Perform the desired task.5. Put the result value in a place where the calling program can
access it.6. Return control to the point of origin, since a procedure can be
called from several points in a program.
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Procedures
I Procedure. A stored subroutine that performs a specific taskbased on the parameters with which it is provided.
I Steps:
1. Put parameters in a place where the procedure can accessthem.
2. Transfer control to the procedure.3. Acquire the storage resources needed for the procedure.4. Perform the desired task.5. Put the result value in a place where the calling program can
access it.6. Return control to the point of origin, since a procedure can be
called from several points in a program.
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Procedures
I MIPS software follows the following convention for procedurecalling in allocating its 32 registers:
I $a0 - $a3: four argument registers in which to passparameters
I $v0 - $v1: two value registers in which to return valuesI $ra: one return address register to return to the point of
origin
I Jump and link instructionI jal ProcedureAddress
I Jump registerI jr $ra
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Procedures
I MIPS software follows the following convention for procedurecalling in allocating its 32 registers:
I $a0 - $a3: four argument registers in which to passparameters
I $v0 - $v1: two value registers in which to return valuesI $ra: one return address register to return to the point of
origin
I Jump and link instructionI jal ProcedureAddress
I Jump registerI jr $ra
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Procedures
Use $a0 to $a3 for parameters
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Procedures
leaf example:
addi $sp, $sp, 12
sw $t1, 8($sp)
sw $t0, 4($sp)
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a2
sub $s0, $t0, $t1
add $v0, $s0, $zero
lw $s0, 0($sp)
lw $t0, 4($sp)
lw $t1, 8($sp)
addi $sp, $sp, 12
jr $ra31 / 33
Nested procedure
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Referencias
William Stallings. Computer Organization and Architecture.Prentice Hall. 1993.
Miles J. Murdocca and Vincent P. Heuring. Principios dearquitectura de computadoras. Prentice Hall.
Hennesy Patterson. Computer organization and Design.
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