micros5 - 1P2014

Sonia H. Contreras Or/z, PhD. Juan Carlos Mar9nez Santos, PhD.

Universidad Tecnológica de Bolívar

Cartagena de Indias

Instruc/on Sets

Outline �  Instruc/on Set Architecture (ISA) �  Instruc/on formats �  Instruc/on representa/on �  Instruc/on types � Number of addresses �  Types of operands � Data types � Design decisions

Instruc/on Set Architecture (ISA) �  An instruc/on is a collec/on of bits that instructs the computer to perform an specific opera/on.

�  The ISA is the complete collec/on of instruc/ons that are understood by the computer

�  Instruc/ons are defined by means of binary codes and are represented by assembly codes.

Instruc/on format

� Opera/on code (Op code): specifies the opera/on to be executed

�  Address: provides a memory address or an address to select a CPU register for sources and results

� Mode: specifies how the address is interpreted � Next Instruc/on Reference

Instruc/on representa/on �  In machine code each instruc/on has a unique bit paSern

�  A symbolic representa/on is used � e.g. ADD, SUB, LOAD

� Operands can also be represented in this way � ADD A,B

� Operands can be in CPU registers, main memory (or virtual memory or cache) or I/O devices

Instruc/on types (1) � Data processing

� Arithme/c � Logic and bit manipula/on � ShiW

� Data transfer (Main memory and I/O) �  Program flow control

Instruc/on types (2)

Number of addresses (1) �  3 addresses

� Operand 1, Operand 2, Result � a = b + c; � May be a forth -‐ next instruc/on (usually implicit)

� Not common � Needs very long words to hold everything

Number of addresses (2) �  2 addresses

� One address doubles as operand and result � a = a + b � Reduces length of instruc/on � Requires some extra work

�  Temporary storage to hold some results

Number of addresses (3) �  1 address

�  Implicit second address � Usually a register (accumulator) � Common on early machines

�  0 (zero) addresses � All addresses implicit � Uses a stack e.g. c=a+b

�  push a �  push b �  add �  pop c

Number of addresses (4) � More addresses

� More complex instruc/ons � More registers

�  Inter-‐register opera/ons are quicker � Fewer instruc/ons per program

�  Fewer addresses � Less complex instruc/ons � More instruc/ons per program � Faster fetch/execu/on of instruc/ons

Types of operands �  Addresses � Numbers

� Integer/floa/ng point �  Characters

� ASCII etc. �  Logical Data

� Bits or flags

Pen/um II data types

Byte order (1) � How to read numbers that occupy more than one byte

�  There are two modes: big-‐endian and liSle-‐endian �  e.g. 12345678 (in Hex) can be stored in 4x8bit loca/ons as follows

Address Big-endian Little-endian

184 12 78

185 34 56

186 56 34

187 78 12

Byte order (2) �  Big-‐endian: the first byte (lower address) has the most significant byte.

�  LiSle-‐endian: the lower address has the least significant byte.

Design decisions (1) � Opera/on repertoire

� How many ops? � What can they do? � How complex are they?

� Data types �  Instruc/on formats

� Length of op code field � Number of addresses

Design decisions (2) �  Registers

� Number of CPU registers available � Which opera/ons can be performed on which registers?

�  Addressing modes (next week) �  RISC vs CISC

Design decisions (3)

RISC CISC

�  Reduced instruc/on set computers

�  Emphasize simple instruc/ons and flexibility

�  Provide higher throughput and faster execu/on

�  Complex instruc/on set computers

�  Provide hardware support for high-‐level language opera/ons

� Have compact programs

Exercises 1.  A pocket pager contains a small processor with 27 8-‐

bit words of memory. The ISA has four registers: R0, R1, R2, and R3. The instrunc/on set is shown next, as well as the bit paSerns that correspond to each register, the instruc/on format, and the modes, which determines if the operand is a register (mode bit = 0) or the operand is a memory loca/on (mode bit = 1). Either or both of the operands can be registers, but both operands cannot be memory loca/ons. If the source or des/na/on is a memory loca/on, the the corresponding source or des/na/on field in the instruc/on is not used since the addess field is used instead.

Exercises a.  Write a program using object code (not assembly

code) that swaps the contents of registers R0 and R1. You are free to use the other registers as necessary, but do not use memory. Use no more than four line of code (fewer lines are possible). Place 0’s in any posi/ons where the value does not maSer.

b.  Write a program using object code that swaps the contents of memory loca/ons 12 and 13. As in part (a), you are free to use the other registers as necessary, but do not use other memory loca/ons. Place 0’s in any posi/ons where the value does not maSer.

Exercises 2.  TODO: a.  Write three-‐address, two-‐address, and one-‐

address programs to compute the func/on A = (B – C) * (D – E).

Assume 8-‐bit opcodes, 16-‐bit operands and addresses, and that data is moved to and from memory in 16-‐bit chunks. (Also assume that the opcode must be transferred from memory by itself). Your code should not overwrite any operands. Use any temporal registers needed.

Exercises

b.  Compute the size of your program in bytes.

c.  Compute the memory traffic your program will generate at execu/on /me, including instruc/on fetches.

micros5 - 1P2014

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