MODELLING OF DIGITAL CIRCUITSUSING

VERILOG HDL

Presented By,Sriram Sundar S

Assistant Professor

Department of E.C.E

CARE GROUP OF INSTITUTIONS 2

• An integrated circuit (IC) is a miniature, low cost electronic circuit consisting of active and passive components fabricated together on a single crystal of silicon.

• The active components are transistors and diodes and passive components are resistors and capacitors.

Integrated Circuits

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CARE GROUP OF INSTITUTIONS 3

• Bardeen, Brattain and Schockley at Bell Labs 1947 fabricated the First Transistor

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• First monolithic (single substrate) IC was fabricated Jack Kilby of Texas Instruments 1958 using Germanium.

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Robert Noyce, 1958 July at Fairchild Semiconductor fabricated the first Silicon monolithic IC.

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VERY LARGE SCALE INTEGRATION

Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (more than millions) of transistors on a single integrated circuit.

VLSI DESIGN FLOW

VLSI Design Flow

VERILOG HARDWARE DESCRIPTION LANGUAGE

• Verilog has come as long way since it started at Gateway Design Automation in 1984

• It is now used extensively in the design of integrated circiuts and digital systems.

• Verilog has been designed to be intuitive and simple to learn, this is why a programmer may see many similarities between Verilog and other popular languages like pascal and C.

• Verilog can closely simulate real circuits using built-in primitives, user-defined primitives, timing checks, pin-to-pin delay simulation and the ability to apply external stimulus to designs enabling testing before synthesis.

• The extension which made Verilog really take off was the Synthesis technology introduced in 1987. This, coupled with Verilog's ability to extensively verify a digital design, enabled quick hardware design

GATE TYPESKeywords: and, nand, or , nor, xor, xnor, buf, not.

and <name><list of arguments>and myand(out, in1, in2, in3); // legal and gate with three inputsand (out, in1, in2); // legal gate with no name. The buf and not gates each have one input and one or more outputs. The conventional is the same, the outputs come first and the last argument in the list is the input. buf mybuf(out1, out2, out3, in); not (out, in);

LEXICOGRAPHY

• White Space and Comments • Operators • Numbers • Strings

Verilog, like any high level language has a number of tokens which we will discuss in this section. Tokens can be comments, delimiters, numbers, strings, identifiers and keywords. All keywords are in lower case.

WHITE SPACE AND COMMENT

White Space The white space characters are space (\b), tabs (\t), newlines (\n). These are ignored except in strings

Comments Two types of comments are supported, single line comments starting with // and multiple line comments delimited by /* ... */. Comments cannot be nested. It is usually a good idea to use single line comments to comment code and multiple lines comments to comment out sections of code when debugging

OPERATORS

Verilog has three types of operators, they take either one, two or three operands. Unary operators appear on the left of their operand, binary in the middle, and ternary separates its three operands by two operators.  clock = ~clock; // ~ is the unary bitwise negation operator, clock is the operandc = a || b; // || is the binary logical or, a and b are the operandsr = s ? t : u; // ?: is the ternary conditional operator, which reads r = [if s is true then t else u]

NUMBERS

Integers Integers can be in binary ( b or B ), decimal ( d or D ), hexidecimal ( h or H ) or octal ( o or O ). Numbers are specified by 1. <size>'<base><number> : for a full description 2. <base><number> : this is given a default size which is machine dependant but at least 32 bits. 3. <number> : this is given a default base of decimal

The size specifies the exact number of bits used by the number. For example, a 4 bit binary will have 4 as the size specification and a 4 digit hexadecimal will have 16 as the size specification since each hexadecimal digit requires 4 bits. 8'b10100010 // 8 bit number in binary representation 8'hA2 // 8 bit number in hexadecimal representation

NUMBERS (Cont..)X and Z values x represents an unknown, and z a high impedance value. An x declares 4 unknown bits in hexadecimal, 3 in octal and 1 in binary. z declares high impedance values similarly. Alternatively z, when used in numbers, can be written as ? This is advised in case expressions to enhance readability. 4'b10x0 // 4 bit binary with 2nd least sig. fig. unknown4'b101z // 4 bit binary with least sig. fig. of high impededance12'dz // 12 bit decimal high impedance number12'd? // 12 bit decimal high impedance 'don't-care' number8'h4x // 8 bit number in hexidecimal representation with the four least significant bits unknown

NUMBERS (Cont..)

Negative numbers A number can be declared to be negative by putting a minus sign infront of the size. The minus sign must appear at the start of a number (in all three formats given above), ie. it must not appear between the size specifier and base, nor between the base and the format specidications. -8'd5 // 2's compliment of 5, held in 8 bits 8'b-5 // illegal syntax

NUMBERS (Cont..)

Underscore Underscores can be put anywhere in a number, except the beginning, to improve readability.

16'b0001_1010_1000_1111 // use of underscore to improve

readability 8'b_0001_1010 // illegal use of underscore

NUMBERS (Cont..)

Real Real numbers can be in either decimal or scientific format, if expressed in decimal format they must have at least one digit either side of the decimal point. 1.8 3_2387.3398_3047 3.8e10 // e or E for exponent 2.1e-9 3. // illegal

STRINGS

Strings are delimited by " ... ", and cannot be on multiple lines.

"hello world"; // legal string "good b y e wo rld"; // illegal string

DATA TYPES

• Nets • Registers • Vectors • Arrays • Tri-state

NETSKeywords: wire, supply0, supply1 default value: z default size: 1 bit

Nets represent the continuous updating of outputs with respect to their changing inputs. For example in the figure below, c is connected to a by a not gate. if c is declared and initialised as shown, it will continuously be driven by the changing value of a, its new value will not have to be explicitly assigned to it. If the drivers of a wire have the same value, the wire assumes this value. If the drivers have different values it chooses the strongest, if the strengths are the same the wire assumes the value of unknown, x.The most frequently used net is the wire, two others which may be useful are supply0, and supply1, these model power supplies in a circuit.

REGISTERSKeywords: regdefault value: xdefault size: 1 bit • The fundamental difference between nets and registers

is that registers have to be assigned values explicitly. That value is held until a new assignment is made. This property can, for example, be used to model a E-type flip flop as shown in figure below, with corresponding Verilog code given below.

• Register q holds the same value until it us changed by an explicit assignment.

VECTORSBoth the register and net data types can be any number of bits wide if declared as vectors. Vectors can be accessed either in whole or in part, the left hand number is always the most significant number in the vector. See below for examples of vector declarations.

reg [3:0] output; // output is a 4-bit register wire [31:0] data; // data is a 32-bit wire reg [7:0] a; data[3:0] = output; // partial assignment output = 4'b0101; // assignment to the whole registerIt is important to be consistant in the ordering of the vector width declaration. Normally the most significant figure is written first. reg [3:0] a; // it is important to adopt one convention for reg [0:3] b; // the declaration of vector width.

TRI-STATE• A tri-state driver is one which will output either HIGH,

LOW or "nothing". • In some architectures, many different modules need to be

able to put data onto (to drive) the same bus, at different times. Thus they all connect to the one common bus - but a set of control signals seek to ensure that only one of them is driving a signal at any one time.

• In Verilog, this is modelled using different signal "strengths". There is a signal value: z, which is called "high-impedance". This basically means that a node is isolated, that is not driven. It is possible to assign this value to a net.

TRI-STATE (CONT..)module triDriver(bus, drive, value);inout [3:0] bus;input drive;input [3:0] value;assign #2 bus = (drive == 1) ? value : 4'bz;endmodule

When the drive signal is high, the bus is driven to the data value, otherwise, this driver outputs only a high-impedance and hence can be over-ridden by any other driven value.

OPERATORS• Arithmetic • Logical • Relational • Equality • Bitwise • Reduction • Shift • Concatenation and Replication

ARITHMETIC OPERATORSkeysymbols: *, /, +, -, % The binary operators are multiply, divide, add, subtract and modulus used as shown in the examples below. (a * b); // multiplication, (a / b); // division, evaluate(a + b); // addition, evaluates to 15(a - b); // subtraction, evaluates to 9((a + 1'b1) % b); // modulus, evaluates to 1

The unary operators are plus and minus, and have higher precedence than binary operators. Note If any bit of an operand is unknown: x, then the result of any arithmetic operation is also unknown.

LOGICAL OPERATORSKeysymbols: &&, ||, !. The logical operators are logical and, logical or and logical not.All logical operators evaluate to either true ( 1 ), false ( 0 ), or unknown ( x ). a = 2; b = 0; c = 4'hx;(a && b); // logical and, evaluates to 0 (a || b); // logical or, evaluates to 1 (!a); // logical not, evaluates to 0 (a || c); // evaluates to 1, unknown || 1 (=1) (!c); // evalutes to unknown

RELATIONAL OPERATORSThe relational operators are less than, more than, less then or equal to and more than or equal to. The true and false values are defined in the same way as above in the logical operator. In this case if any operand is unknown the whole expression evaluates to unknown. See examples below.

a=2; b=5; c=2; d=4'hx;(a < b); // LHS less than RHS, evaluates to true, 1(a > b); // LHS more than RHS, evaluates to false, 0(a >= c); // more than or equal to, evaluates to true, 1(d <= a); // less than or equal to, evaluates to unknown

EQUALITYkeysymbols: ==, !=, ===, !==.

The equality operators are logical equality, logical inequality, case equality and case inequality. These operators compare the operands bit-by-corresponding-bit for equality.

The logical operators will return unknown if "significant" bits are unknown or high-impedence (x or z)

The case operators look for "equality" also with respect to bits which are unknown or high impedence.

If one operand is shorter than the other, it is expanded with 0s unless the most significant bit is unknown.

EQUALITY (CONT..)a = 4; b = 7; // these default to decimal bases

c = 4'b010; d = 4'bx10; e = 4'bx101; f = 4'bxx01;

$display(c); // outputs 0010

$display(d); // outputs xx10

$display(a == b); // logical equality, evaluates to 0

$display(c != d); // logical inequality, evaluates to x

$display(c != f); // logical inequality, evaluates to 1

$display(d === e); // case equality, evaluates to 0

$display(c !== d); // case inequality, evaluates to 1

BITWISE OPERATORSkeysymbols: ~, &, |, ^, (~^, ^~).

The bitwise operators are negation, and, or, xor and xnor. Bitwise operators perform a bit-by-corresponding-bit operation on both operands, if one operand is shorter it is bit extended to the left with zeros. See examples below.

a = 4'b1100; b = 4'b0011; c = 4'b0101; $displayb(~a); // bitwise negation, evaluates to 4'b0011 $displayb(a & c); // bitwise and, evaluates to 4'b0100 $displayb(a | b); // bitwise or, evaluates to 4'b1111 $displayb(b ^ c); // bitwise xor, evaluates to 4'b0110 $displayb(a ~^ c); // bitwise xnor, evaluates to 4'b0110

REDUCTION OPERATORKeysymbols: &, ~&, |, ~|, ^, ~^, ^~.

The reduction operators are and, nand, or, nor, xor xnor and an alternative xnor. They take one operand and perform a bit-by-next-bit operation, starting with the two leftmost bits, giving a 1-bit result.

a = 4'b1111; b = 4'b0101;c = 4'b0011;

$displayb(& a); // bitwise and, (same as 1&1&1&1), evaluates to 1$displayb(| b); // bitwise or, (same as 0|1|0|1), evaluates to 1$displayb(^ b); // bitwise xor, (same as 0^1^0^1), evaluates to 0

Note: the bitwise xor and xnor are useful in generating parity checks.

TYPES OF MODELLING1. Behaviour Modelling2. Dataflow Modelling3. Structural Modelling

- Gate Level Modelling

DATAFLOW MODELLINGOR Gate

module or_gate_dataflow(out,x,y);input x,y;output out;assign or_out = x|y;endmodule

BEHAVIOUR LEVEL MODELLING

module or_behav(y,a,b);output y;input a,b;reg y;always @ (a or b)begin

if (a = = 0)begin

if (b = = 0)y = 1 'b 0;elsey = 1 'b 1;

endelse

y = 1 'b1;endendmodule

GATE LEVEL MODELLINGOR Gate

module or_gate_dataflow(out,x,y);input x,y;output out;or g1(out,x,y) ;endmodule

SWITCH LEVEL MODELLINGNAND Gate

module nand_gate(y,a,b);input a,b;output y;wire out;Supply1 VDD;Supply0 gnd;pmos p1(VDD,y,a);pmos p2(VDD,y,b);nmos n1(gnd,out,b);nmos n2(out,y,a);endmodule

MULTIPLEXER

Inputs Select Lines OutputSel1 Sel0 Y

d0 0 0 d0

d1 0 1 d1

d2 1 0 d2

d3 1 1 d3

Y 013012011010 SelSeldSelSeldSelSeldSelSeld

MULTIPLEXER

5 BIT RIPPLE CARRY ADDER

4 BIT MULTIPLIER a3 a2 a1 a0

b3 b2 b1 b0

a3b0 a2b0 a1b0 a0b0

a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2 a3b3 a2b3 a1b3 a0b3 o7 o6 o5 o4 o3 o2

o1a0b0 = p0 a1b2 = p8a1b0 = p1 a0b3 = p9a0b1 = p2 a3b1 = p10a2b0 = p3 a2b2 = p11a1b1 = p4 a1b3 = p12a0b2 = p5 a3b2 = p13a3b0 = p6 a2b3 = p14a2b1 = p7 a3b3 = p15

4 BIT MULTIPLIER

HAFA HAHA

HA

FAFAFA

FA

FA

FAFA

P0

O0

P2 P1

O1

P4 P3P7 P6P11,P10P14 P13

P15

O2O3O4O5O6O7

P8

P9

P12

PRBS GENERATOR

COUNTER

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