G.Albareda , D.Jimenez and X.Oriols Universitat Autònoma de Barcelona - Spain

UPoN Lyon 2008UPoN Lyon 2008 G. AlbaredaG. Albareda 1

G.Albareda, D.Jimenez and X.OriolsUniversitat Autònoma de Barcelona - Spain

E.mail: [email protected]

Can analog and digital applications tolerate the intrinsic noise for aggressively scaled field-effect

transistors?

Lyon, FRANCE June 2-6, 2008


I.1.- Intrinsic noise in ballistic nanoscaleFETs

I.2.- Analytical Signal-to-noise ratio (S/N)

II.- Monte Carlo simulation of 3D, 2D and 1D FETs

III.- Conclusions

I.3.- Analytical Bit-error ratio (BER)

I.- Introduction: 3D, 2D and 1D ballistic nanoscale FETs

Outline

II.1.- Simulator description

II.2.- Numerical results


I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs

The size of the transistors shrinks for faster and smaller microchips

Ly

Lz

Lx

1,2,3,4 gates to improve gate control (Lx>Ly,Lz)

When Ly and Lz become comparable to the electron de Broglie wavelength, the wave-nature of the electron is manifested.

Ly Lz

3D Bulk FET

BB

Ly Lz

2D Quantum Well FET

BB

Ly Lz

1D Quantum-Wire FET

BB

x z

y

1,2,3,4 gates to improve gate control (Lx>Ly,Lz)


I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs

Study the noise performance of these aggressively scaled FET in analog and digital circuit applications

We only consider the “intrinsic” sources of noise due to electron-electron interactions (intrinsic field-effect)

We consider ballistic (“ideal”) FETs: No phonon scattering No surface roughness

No impurity scattering

OUR GOAL

.- The Coulomb interaction in the active region

I(t)

.- Exclusion (Pauli) interaction in the contacts


I.2.- Signal to noise ratio (S/N)

RL

Analog FET amplifier

0,0 0,2 0,4 0,6 0,8 1,0 1,2

0

1

2

3

4

5

6

VD>VDS

VG>VGS

Sub-thresohold region

Curr

ent (

)

Drain Voltage (V)

G 0

3D 30 x 10 x 8 nm3


RLRL


Analog FET amplifier

DS DS DSI t I t G V

In the saturation region G0:

Using the superposition principle:

2

2L

D LR DS

D L

R RN qI F B

R R

222

2 2L

CC CCD LR DS DS

D DD L

V VR RS I I

R RR R

0

2I

DS

SF

e I

For D LR R

1

2L

L

R DS

R

S I

N qB F

NS

D

S

IDS(t) IDS(t)G

IDS(t)

IDS(t)



Eq

)(EfI

max_Ec

)(1)·()0( EfEfS

Ef

The role of electron confinement on the average and noise current

Ly

Lz

Lx

S D

1

2L

L

R DS

R

S I

N qB F

max_EcEf

S D

21

0DSL

L

R

R

IS

N S B

S/N3D > S/N1D


VCC

‘1’

VCC

‘0’

ON

ONOFF

OFF

‘1’

noisy

noislessP P

N NNN

Digital FET inverter:

Vi

VoVth

V

0 1

Bit error ratio (BER):

I.3.- Bit error ratio (BER) in digital applications

0,0 0,2 0,4 0,6 0,8 1,0 1,20

1

2

3

4

5

6

VD>VDS

VG>VGS


Cur

rent

(

)

Drain Voltage (V)

IDS(t) 0NS

D

S

IDS(t) IDS(t)G

C


NS

D

S

IDS(t) IDS(t)G C

VCC

‘1’

VCC

‘0’

ON

ONOFF

OFF

‘1’

noisy

noislessP P

N NNN

I.3.- Bit error ratio (BER) in digital applications

Thermal noise: (0) (0) (0) 4· · ·I S D BS S S k T G

Voltage fluctuations: 1 1

1DS

T

V IC

jR C

Noise Power: 1410 tan 2B

V c T

k TN f R C

C

Vi

VoVth

V

0 1

Bit error ratio (BER):

A/2

[ref] L.B.Kish, Physics Letters A 305 (2002) 144-149.

IDC

C3D > C1D

BER3D < BER1D


II.- Monte Carlo simulation of 3D, 2D and 1D FETs

III.- Conclusions

I.- Introduction: 3D, 2D and 1D nanoscale FETs

Outline

II.1.- Simulator description:

II.2.- Numerical results:

II.2.1.- Average current II.2.2.- Signal to noise ratio

II.2.3.- Bit error ratio

II.1.1.- Confined particles in 1D FETs II.1.2.- Exact 3D Coulomb interaction

II.1.3.- Electron injection model with “Pauli” correlations and charge neutrality


1-D

eVeVE

Em

kE

qD

qD

t

x

08.01.0

·2

1

1

22

No electron confinement

Ly

Lz

Lx

z

y

Silicon (100) channel orientation Lx=15 nm Ly=5 nm Lz=2 nm

Quantum potential for the x systemGuess: 0

0

z

y

v

v

elsewhere

LxEttztyxQ x

qD

yx0

0)),(),(,( 1

This guess is quite accurate when there is only one relevant quantized energy

II.1.1.- Confined particles in 1D FETs

1qDE

xy

E

[ref] X.Oriols, Physical Review Letters, 98, 066803 (2007)


II.1.2.- Exact 3D Coulomb interaction

3D Coulomb interaction beyond the mean-field approximation

[ref] G.Albareda et al, J. Comp. Electr. (2008)

DX

ERROR

Long-rangeLong-rangeLong-rangeLong-range ++Short-Short-rangerange # e- per cell > 1

# e- per cell = 0 or 1

1nm-5nm1nm-5nm

mean-field (1 Poisson Eq.)

exact-field (N Poisson Eqs.)

kk

extk

kjkkfieldmean rU

r

q

jkmH

0

22

*

2

"" 42

1

2

Long-rangeLong-range

• Mean-field SEPARABLE• Exact termNOT SEPARABLE

k

kextk

kjjk

kkexact rU

rq

jkmH

0

22

*

2

421

2

Long-range + Short-rangeLong-range + Short-range


)/()(exp1

1)(

TkEEEf

Bf

t

I(t) e e e

Temperature ; T>0

0

Binomial injection process

ot

Pauli correlation

[ref] X.Oriols et al. Solid State Electronics, 51, 306 (2007)

[ref] T.Gonzalez, Semicond. Sci. Technol. 14, L37 (1999)

II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality

0 ##D

( , , , , )x y z D

tt y z k k k

n

Time-dependent version of Landauer-Buttiker boundary conditions


Our injection model, coupled to the boundary conditions of the Poisson equation, does also assures charge neutrality at the contacts

,, 0

d r tr t

dt

,C DE N x n t x

, ,J t r E t r

,,

t rE t r

For a good conductor

Local Gauss equation

0Jt

Continuity equation

Practical Monte Carlo implementation

II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality

t

[ref] H.Lopez, G.Albareda et al., J. Comp. Electr. (2008)

=/

Charge neutrality

At each time step:


II.2.1.- Average current

Average current

No scaling rule: SiO2 oxide thickness: tox=2 nm Contact doping: 2·1019cm-3

Vdrain

Vgate

Vgate

0,0 0,2 0,4 0,6 0,8 1,0 1,20369

121518212427303336

Curr

ent (

)

Drain Voltage (V)

VG>VGS


VD>VDS

0,0 0,2 0,4 0,6 0,8 1,0 1,20

1

2

3

4

5

6

VD>VDS

VG>VGS


Curr

ent (

)

Drain Voltage (V)

3D 30 x 10 x 8 nm3 1D 15 x 5 x 2 nm3=0.5V =0.35V

‘0’0V ‘1’0.5V


II.2.2.- Signal-to-noise ratio

Amplifying configuration (saturation region)

S/N comparison

FI

BqNS

··21

/

-0,1 0,0 0,1 0,2

106

107

108

1D 3D

Sig

nal-to

-Nois

e r

atio

S/N

Gate Voltage (V)

MHzB 1

Vdrain=0.5 V

Vgate

Vgate

-0.1 0.0 0.1 0.2

5

10

15

20

25

30

Fano F

actor

Dra

in C

urre

nt (

)

Gate Voltage (V)

0.5

0.6

0.7

0.8

0.9

1.0

3D 1D

3D Average current > 1D Average current3D Fano Factor < 1D Fano Factor


2 3 4 5

-0,3

-0,2

-0,1

0,0

0,1

0,2

0,3

Dra

in V

olta

ge (V

)

Time (ps)

Vgate=0.5 V

Vgate=0.5 V

Efd

ECd

Efs

ECs

II.2.3.- Bit-error-degradation

BER error probability

101

DS

QV

C

5ns simulations (time step=2·10-16)


II.2.3.- Bit-error-degradation

BER error probability

Vgate=0.5 V

Vgate=0.5 V

0.5 ; 0.0on offV V V V

-0,4 -0,2 0,0 0,2 0,410-1310-1210-1110-1010-910-810-710-610-510-410-310-210-1100101

dP/d

V

Drain Voltage (V)-0,4 -0,2 0,0 0,2 0,4

10-1310-1210-1110-1010-910-810-710-610-510-410-310-210-1100101

dP

/dV

Drain Voltage (V)

-0,4 -0,2 0,0 0,2 0,410-1310-1210-1110-1010-910-810-710-610-510-410-310-210-1100101

dP

/dV

Drain Voltage (V)

-0,4 -0,2 0,0 0,2 0,410-1310-1210-1110-1010-910-810-710-610-510-410-310-210-1100101

dP

/dV

Drain Voltage (V)

1D3D

50GHz500GHz

1THz 1THz

500GHz50GHz

5THz 5THz

C=5·10-18F C=1·10-18F

Our 3D FETs can hold frequencies up to 500GHz

Our 1D FETs can’t hold frequencies of 500GHz

According to our analitycal estimation, smaller FETs (capacitors) are noisier.


III.- Conclusions

Merci beaucoup

We have developed an accurate Monte Carlo simulator for 3D, 2D and 1D nanoscale FET.

For analog applications, smaller devices produce a minor average current and a larger Fano factor, leading to a signal-to-noise (S/N) degradation.

For digital applications, smaller devices are more sensible to electrostatics (i.e. smaller capacitance), and provide a degradation of the Bit Error Ratio (BER).

In summary, Smaller FETs are noiser for either analog or digital applications.

G.Albareda , D.Jimenez and X.Oriols Universitat Autònoma de Barcelona - Spain

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