Monociclo MIPS-VHDL tercer entrega arquitectura de computadores

DLX – MICROPROCESADOR (DATAPATH 3)

RESUMEN

Este informe describe los componentes básicos para la implementación de un microprocesador, basándose en el anterior taller (DATAPATH 2), se crearon nuevos módulos fueron y necesitaras varias modificaciones de módulos existente para la implementación de este nuevo dispositivo (DATAPATH 3) que dispone de un set de instrucciones más completo. Este taller será implementado en una FPGA.

PALABRAS CLAVES: VHDL, FPGA, microprocesador, dispositivo, implementación, instrucciones.

ABSTRACTThis report described the basic components for the implementation of a microprocessor basing in lastest workshop DATAPATH 2, new modules are created and may be changes in some existent modules for the implementation of this new device (DATAPATH3) that develops a Set of more complete instructions, and than finally will be implemented in the FPGA.

KEYWORDS: MIPS, VHDL, FPGA, MICROPROCESSOR

,.

JUAN PABLO GARCÍAIng. de Sistemas y ComputaciónEstudiante VII SemestreUniversidad Tecnológica de [email protected]

JUAN PABLO GÓMEZIng. Sistemas y ComputaciónEstudiante VII SemestreUniversidad Tecnológica de [email protected]

1. INTRODUCCIÓN

Este tercer taller es la implementación final del procesador monociclo, fueron necesarios los conocimientos de las asignaturas de arquitectura de computadores y de lab de arquitectura. El comportamiento del datapath será descrito módulo por módulo en el presente informe. Solo serán descritos aquellos módulos del datapath 2 que fueron modificados, y aquellos nuevos módulos. el cual, comparado con el DATAPATH2, contiene un set de instrucciones más completo, con las cuales se puede implementar un programa para lenguaje ensamblador MIPS.

2. CONTENIDO

1. Memoria de Datos

DescripciónEs una memoria que permite almacenar temporalmente datos, como si fuera una memoria del sistema.

Código

entity DataMem is Port ( i_addr : in STD_LOGIC_VECTOR (31 downto 0); i_din : in STD_LOGIC_VECTOR (31 downto 0);

i_clk : in STD_LOGIC; i_we : in STD_LOGIC; o_dat : out STD_LOGIC_VECTOR (31 downto 0));end DataMem;

architecture Behavioral of DataMem is

type RAM_type is array (0 to 511) of std_logic_vector(31 downto 0);signal RAM : RAM_type;signal addr_temp: STD_LOGIC_VECTOR (31 downto 0);

beginprocess (i_clk, i_addr)begin

addr_temp <= i_addr;if (rising_edge(i_clk)) then

o_dat <= RAM(conv_integer(addr_temp(10 downto 2)));

if (i_we = '1') thenRAM(conv_integer(addr_temp(10 downto 2)))

<= i_din;end if;

end if;end process;

end Behavioral;

DLX–MICROPROCESADOR(DATAPATH 3) Noviembre/2006/6

2. Controlador de Program Counter:

Descripción

Recibe un tipo de salto y permite seleccionar que señal recibe el program counter.

Código

entity pccontrol is Port ( i_pcsel : in STD_LOGIC_VECTOR (1 downto 0); i_eq : in STD_LOGIC; o_pcsel : out STD_LOGIC_VECTOR (1 downto 0));end pccontrol;

architecture Behavioral of pccontrol is

beginprocess (i_pcsel, i_eq)begin

if (i_pcsel = "00") then -- cualquier instrucciono_pcsel <= "00";

elsif (i_pcsel = "01") then -- BEQif (i_eq = '1') then

o_pcsel <= "01";else

o_pcsel <= "00";end if;

elsif (i_pcsel = "10") then -- Jo_pcsel <= "10";

elsif (i_pcsel = "11") then -- BNEif (i_eq = '1') then

o_pcsel <= "00";else

o_pcsel <= "11";end if;

end if;

end process;

end Behavioral;

3. Entendedor de Jump (de 26 bits a 32 bits):

Descripción

Recibe el numero de 26 bits de la instrucción J y lo convierte a un numero de 32 bits .

Código

entity ext26b is Port ( i_dat : in STD_LOGIC_VECTOR (25 downto 0);

o_ext : out STD_LOGIC_VECTOR (31 downto 0));end ext26b;

architecture Behavioral of ext26b is

beginprocess (i_dat)begin

if (i_dat(25) = '1') theno_ext <= b"1111" & i_dat & b"00";

elseo_ext <= b"0000" & i_dat & b"00";

end if;

end process;

end Behavioral;

4. Decodificador de Opcodes (modificado):

Descripción

Permite controlar las diferentes señales del sistema dependiendo de la instrucción a la que es sometido.

Código

entity decopcode is Port ( i_opcode : in std_logic_vector(5 downto 0); i_funct : in std_logic_vector(5 downto 0); o_aluctrl : out std_logic_vector(3 downto 0); o_alusrc : out std_logic; o_regdest : out std_logic;

o_regwr : out std_logic; o_memwr : out std_logic; o_memtoreg : out std_logic; o_pcsrc : out std_logic_vector(1

downto 0)); -- 00 si contador regular, 01 si BEQ, 10 si J, 11 si reset.end decopcode;

architecture Behavioral of decopcode is

beginprocess (i_opcode, i_funct)begin

case i_opcode iswhen "000000" => -- tipo R

case i_funct iswhen "000000" => o_aluctrl <= "1001"; -- SLLwhen "000010" => o_aluctrl <= "1010"; -- SRLwhen "100100" => o_aluctrl <= "0000"; -- ANDwhen "100101" => o_aluctrl <= "0001"; -- ORwhen "100001" => o_aluctrl <= "0010"; --

ADDU, era ADD (100000)

____________________________


when "100011" => o_aluctrl <= "0110"; -- SUBU, era SUB (100010)

when "101010" => o_aluctrl <= "0111"; -- SLTwhen "100110" => o_aluctrl <= "1100"; -- XORwhen others => o_aluctrl <= "0000";end case;o_alusrc <= '0';o_regdest <= '1';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "000010" => o_aluctrl <= "0000"; -- Jo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '0';o_pcsrc <= "10";

when "000100" => o_aluctrl <= "0000"; -- BEQo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '0';o_pcsrc <= "01";

when "000101" => o_aluctrl <= "0000"; -- BNEo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '0';o_pcsrc <= "11";

when "001100" => o_aluctrl <= "0000"; -- ANDIo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "001101" => o_aluctrl <= "0001"; -- ORIo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "001001" => o_aluctrl <= "0010"; -- ADDIUo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "001010" => o_aluctrl <= "0111"; -- SLTIo_alusrc <= '1';

o_regdest <= '0';o_memwr <= '0';

o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "001110" => o_aluctrl <= "1100"; -- XORIo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '0';o_regwr <= '1';o_pcsrc <= "00";

when "100011" => o_aluctrl <= "1111"; -- LWo_alusrc <= '1';o_regdest <= '0';o_memwr <= '0';o_memtoreg <= '1';o_regwr <= '1';o_pcsrc <= "00";

when "101011" => o_aluctrl <= "1111"; -- SWo_alusrc <= '1';o_regdest <= '0';o_memwr <= '1';o_memtoreg <= '1';o_regwr <= '0';o_pcsrc <= "00";

when others => o_aluctrl <= "0000"; -- o_alusrc <= '1';o_regdest <= '0';o_memwr <= '1';o_memtoreg <= '1';o_regwr <= '0';o_pcsrc <= "00";

end case;end process;

end Behavioral;

5. ALU (Modificada):

Descripción

Este componente realiza los calculos lógicos que se requieren por las operaciones soportadas por el sistema.

Código

entity alu32b is Port ( in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0);

in_s : in std_logic_vector(4 downto 0); in_funct : in std_logic_vector(3 downto 0); o_y : out std_logic_vector(31 downto 0);

o_eq : out std_logic);end alu32b;

architecture Behavioral of alu32b is

____________________________


beginprocess (in_a, in_b, in_funct)begin

case in_funct iswhen "0000" => o_y <= in_a AND in_b;when "0001" => o_y <= in_a OR in_b;when "0010" => o_y <= in_a + in_b;when "0110" => o_y <= in_a - in_b;when "0111" => if (in_a < in_b) then

o_y <= (others => '1');else o_y <= (others => '0');end if;when "1100" => o_y <= in_a XOR in_b;when "1001" => case in_s iswhen "00000" => o_y <= in_b;when "00001" => o_y <= in_b(30 downto 0) &

'0';when "00010" => o_y <= in_b(29 downto 0) &

"00";when "00011" => o_y <= in_b(28 downto 0) &






"00000000";

when "01001" => o_y <= in_b(22 downto 0) & "000000000";






















when "11111" => o_y <= in_b(0) & "0000000000000000000000000000000";

when others => o_y <= in_b(0) & "0000000000000000000000000000000";

end case;when "1010" => case in_s iswhen "00000" => o_y <= in_b;when "00001" => o_y <= '0' & in_b(30 downto

0);when "00010" => o_y <= "00" & in_b(29

downto 0);when "00011" => o_y <= "000" & in_b(28

downto 0);when "00100" => o_y <= "0000" & in_b(27

downto 0);

when "00101" => o_y <= "00000" & in_b(26 downto 0);











____________________________

















when "11111" => o_y <= "0000000000000000000000000000000" & in_b(0);

when others => o_y <= "0000000000000000000000000000000" & in_b(0);

end case;when "1111" => o_y <= in_a;when others => o_y <= (others => '1');end case;

if (in_a = in_b) theno_eq <= '1';

elseo_eq <= '0';

end if;end process;

end Behavioral;

6. Modulo principal (DATAPATH 3):

Descripción

Es el modulo principal de todo el sistema .

Código

entity Datapath3 is Port ( i_clk : in std_logic; i_rst : in std_logic;

i_we : in std_logic; i_sel : in std_logic_vector(1 downto

0); o_output: out std_logic_vector(7

downto 0); o_prueba: out std_logic_vector(3

downto 0));end Datapath3;

architecture Structural of Datapath3 is

component Datapath1 is Port ( i_rst : in std_logic; i_clk : in std_logic;

i_en : in std_logic; i_eq : in std_logic; i_pcsrc : in std_logic_vector(1 downto

0); i_offset : in std_logic_vector(25

downto 0); o_data : out std_logic_vector(31 downto 0));end component;

component Regfile isport(i_wd : in std_logic_vector(31 downto 0);

-- Input Data i_ws : in std_logic_vector(4 downto 0);

-- Input Address i_rs1 : in std_logic_vector(4 downto 0);

-- Output Address 1 i_rs2 : in std_logic_vector(4 downto 0);

-- Output Address 2 i_we : in std_logic; -- Write Enable i_clk : in std_logic;

-- Global Clk

o_rd1 : out std_logic_vector(31 downto 0); -- Output Data 1

o_rd2 : out std_logic_vector(31 downto 0) -- Output Data 2

);end component;

component alu32b is Port ( in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0);

in_s : in std_logic_vector(4 downto 0);

____________________________


in_funct : in std_logic_vector(3 downto 0); o_y : out std_logic_vector(31 downto 0);

o_eq : out std_logic);end component;

component decopcode is Port ( i_opcode : in std_logic_vector(5 downto 0); i_funct : in std_logic_vector(5 downto 0); o_aluctrl : out std_logic_vector(3 downto 0); o_alusrc : out std_logic; o_regdest : out std_logic;

o_regwr : out std_logic; o_memwr : out std_logic; o_memtoreg : out std_logic; o_pcsrc : out std_logic_vector(1

downto 0));end component;

component extimmed is Port ( i_immed : in STD_LOGIC_VECTOR (15 downto 0); o_ext : out STD_LOGIC_VECTOR (31 downto 0));end component;

component mux32b2a1 is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); i_sel : in STD_LOGIC; o_y : out STD_LOGIC_VECTOR (31 downto 0));end component;

component mux5b2a1 is Port ( i_a : in STD_LOGIC_VECTOR (4 downto 0); i_b : in STD_LOGIC_VECTOR (4 downto 0); i_sel : in STD_LOGIC; o_y : out STD_LOGIC_VECTOR (4 downto 0));end component;

component div_frec is Port ( i_clk : in STD_LOGIC; i_rst : in STD_LOGIC; o_clk : out STD_LOGIC);end component;

component mux8b4a1 is Port ( i_d0 : in STD_LOGIC_VECTOR (7 downto 0); i_d1 : in STD_LOGIC_VECTOR (7 downto 0);

i_d2 : in STD_LOGIC_VECTOR (7 downto 0); i_d3 : in STD_LOGIC_VECTOR (7 downto 0); i_sel : in STD_LOGIC_VECTOR (1 downto 0); o_y : out STD_LOGIC_VECTOR (7 downto 0));end component;

component DataMem is Port ( i_addr : in STD_LOGIC_VECTOR (31 downto 0); i_din : in STD_LOGIC_VECTOR (31 downto 0); i_clk : in STD_LOGIC; i_we : in STD_LOGIC; o_dat : out STD_LOGIC_VECTOR (31 downto 0));end component;

signal instruccion: std_logic_vector(31 downto 0);signal alures: std_logic_vector(31 downto 0);signal aluoper: std_logic_vector(3 downto 0);signal alusrc, regdest, regwr, memwr, memtoreg, alueq: STD_LOGIC;signal pcsrc : std_logic_vector(1 downto 0);signal add_ws: std_logic_vector(4 downto 0);signal dat_rd1, dat_rd2, dat_ext, dat_alu, dat_mem, dat_2reg: std_logic_vector(31 downto 0);signal nuevoclk: std_logic;

begin

datapath: Datapath1 port map(i_rst => i_rst, i_clk => nuevoclk, o_data => instruccion, i_en => i_we, i_pcsrc => pcsrc, i_offset => instruccion(25 downto 0), i_eq => alueq);decopcod: decopcode port map(i_opcode => instruccion(31 downto 26), i_funct => instruccion(5 downto 0), o_aluctrl => aluoper, o_alusrc => alusrc, o_regdest => regdest, o_memwr => memwr, o_memtoreg => memtoreg, o_pcsrc => pcsrc, o_regwr => regwr);muxde5b: mux5b2a1 port map(i_a => instruccion(20 downto 16), i_b => instruccion(15 downto 11), i_sel => regdest, o_y => add_ws);extinmed: extimmed port map(i_immed => instruccion(15 downto 0), o_ext => dat_ext);regfle: Regfile port map(i_ws => add_ws, i_wd => dat_2reg, i_rs1 => instruccion(25 downto 21), i_rs2 => instruccion(20 downto 16), i_we => regwr, i_clk => nuevoclk, o_rd1 => dat_rd1, o_rd2 => dat_rd2);muxde32b: mux32b2a1 port map(i_a => dat_rd2, i_b => dat_ext, i_sel => alusrc, o_y => dat_alu);

____________________________


alu: alu32b port map(in_a => dat_rd1, in_b => dat_alu, in_s => instruccion(10 downto 6), in_funct => aluoper, o_y => alures, o_eq => alueq);datam : DataMem port map(i_addr => alures, i_din => dat_rd2, i_clk => nuevoclk, i_we => memwr, o_dat => dat_mem);divfrec: div_frec port map(i_clk => i_clk, i_rst => i_rst, o_clk => nuevoclk);muxreg : mux32b2a1 port map(i_a => alures, i_b => dat_mem, i_sel => memtoreg, o_y => dat_2reg);muxde8b: mux8b4a1 port map(i_d0 => alures(7 downto 0), i_d1 => alures(15 downto 8), i_d2 => alures(23 downto 16), i_d3 => alures(31 downto 24), i_sel => i_sel, o_y => o_output);

process (aluoper)begin

o_prueba <= aluoper;end process;

end Structural;

CONCLUSIONES Y RECOMENDACIONES

El sistema tiene algunos problemas, principalmente basados en las operaciones de salto, ya que toman un ciclo adicional para realizarse, sin comprometer los resultados de las operaciones.

Aunque el shift fue optimizado por el sintetizador, la forma en que se aplicó es una manera muy poco optimizada para realizarse.

De resto, el sistema es capaz de incorporar todas las demás funciones, sin problemas.

BIBLIOGRAFIA

*http://isc.utp.edu.co/~michaelm/*MIPS Instruction Set Referente, http://www.mips.com/

____________________________

Monociclo MIPS-VHDL tercer entrega arquitectura de computadores

Documents

Transcript of Monociclo MIPS-VHDL tercer entrega arquitectura de computadores