Unit3_ Ch1 COA

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1Basic Computer Organization & Design

Computer Organization Computer Architectures Lab

BASIC COMPUTER ORGANIZATION AND DESIGN

Instruction Codes

Computer Reisters

Computer Instructions

Timin !nd Contro"

Instruction C#c"e

Memor# Re$erence Instructions

Input%Output !nd Interrupt

Comp"ete Computer Description

Desin o$ B!sic Computer

Desin o$ Accumu"!tor &oic

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'Basic Computer Organization & Design


INTRODUCTION

E(er# di$$erent processor t#pe )!s its o*n desin +di$$erent

reisters, -uses, microoper!tions, m!c)ine instructions, etc. Modern processor is ! (er# comp"e/ de(ice

It cont!ins M!n# reisters

Mu"tip"e !rit)metic units, $or -ot) inteer !nd $"o!tin point c!"cu"!tions

T)e !-i"it# to pipe"ine se(er!" consecuti(e instructions to speed e/ecution Etc0

o*e(er, to underst!nd )o* processors *or2, *e *i"" st!rt*it) ! simp"i$ied processor mode"

T)is is simi"!r to *)!t re!" processors *ere "i2e 3'4 #e!rs !o

M0 Morris M!no introduces ! simp"e processor mode" )e c!""st)e Basic Computer

5e *i"" use t)is to introduce processor or!ni6!tion !nd t)ere"!tions)ip o$ t)e RT& mode" to t)e )i)er "e(e" computerprocessor

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TE BASIC COMPUTER

T)e B!sic Computer )!s t*o components, ! processor !ndmemor#

T)e memor# )!s 89:; *ords in it

89:; < '1', so it t!2es 1' -its to se"ect ! *ord in memor#

E!c) *ord is 1; -its "on

CPU RAM9

89:4

914

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INSTRUCTIONS

Instruction codes

Pror!m

A se=uence o$ +m!c)ine. instructions

+M!c)ine. Instruction

A roup o$ -its t)!t te"" t)e computer toperform a specific operation+!

se=uence o$ micro%oper!tion.

T)e instructions o$ ! pror!m, !"on *it) !n# needed d!t!!re stored in memor#

T)e CPU re!ds t)e ne/t instruction $rom memor#

It is p"!ced in !n Instruction Register+IR.

Contro" circuitr# in contro" unit t)en tr!ns"!tes t)e

instruction into t)e se=uence o$ microoper!tionsnecess!r# to imp"ement it

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INSTRUCTION >ORMAT

Instruction codes

A computer instruction is o$ten di(ided into t*o p!rts An opcode+Oper!tion Code. t)!t speci$ies t)e oper!tion $or t)!t

instruction

An addresst)!t speci$ies t)e reisters !nd?or "oc!tions in memor# touse $or t)!t oper!tion

In t)e B!sic Computer, since t)e memor# cont!ins 89:; +99 Input c)!r!cter to ACOUT >899 Output c)!r!cter $rom ACSHI >'99 S2ip on input $"!SHO >199 S2ip on output $"!ION >99 Interrupt on

IO> >989 Interrupt o$$

Instructions

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1;Basic Computer Organization & Design


INSTRUCTION SET COMP&ETENESS

Instruction T#pes

A computer s)ou"d )!(e ! set o$ instructions so t)!t t)e user c!nconstruct m!c)ine "!nu!e pror!ms to e(!"u!te !n# $unction

t)!t is 2no*n to -e comput!-"e0

>unction!" Instructions

% Arit)metic, "oic, !nd s)i$t instructions

% ADD, CMA, INC, CIR, CI&, AND, C&ATr!ns$er Instructions

% D!t! tr!ns$ers -et*een t)e m!in memor#

!nd t)e processor reisters

% &DA, STA

Contro" Instructions

% Pror!m se=uencin !nd contro"

% BUN, BSA, ISZ

Input?Output Instructions

% Input !nd output

% INP, OUT

Instructions

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CONTRO& UNIT

Instruction codes

Contro" unit +CU. o$ ! processor tr!ns"!tes $rom m!c)ine

instructions to t)e contro" sin!"s $or t)e microoper!tionst)!t imp"ement t)em

Contro" units !re imp"emented in one o$ t*o *!#s

!ard'iredContro" CU is m!de up o$ se=uenti!" !nd com-in!tion!" circuits to ener!te t)e

contro" sin!"s

(icroprogrammedContro"

A contro" memor# on t)e processor cont!ins micropror!ms t)!t!cti(!te t)e necess!r# contro" sin!"s

5e *i"" consider ! )!rd*ired imp"ement!tion o$ t)e contro"unit $or t)e B!sic Computer

1Basic Computer Organization & Design Timin

g and control

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TIMING AND CONTRO&

Contro" unit o$ B!sic Computer

Timing and control

Instruction reister +IR.

14 18 17 1' 11 % 9

7 / decoder

; 4 8 7 ' 1 9

I

D9

14 18 0 0 0 0 ' 1 98 / 1;

decoder

8%-itse=uence

counter+SC.

Increment +INR.

C"e!r +C&R.

C"oc2

Ot)er inputs

Contro"sin!"s

D

T

T

14

9

Com-in!tion!"Contro"

"oic

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g and control

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1:Basic Computer Organization & Design


TIMING SIGNA&S

Clock

T0 T1 T2 T3 T4 T0

T0

T1

T2

T3

T4

D3

CLR

SC

% Gener!ted -# 8%-it se=uence counter !nd 8

1; decoder% T)e SC c!n -e incremented or c"e!red0

% E/!mp"e@ T9, T1, T', T7, T8, T9, T1, 0 0 0

Assume@ At time T8, SC is c"e!red to 9 i$ decoder output D7 is !cti(e0

D7T8@ SC 9

Timing and control

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INSTRUCTION CC&E

In B!sic Computer, ! m!c)ine instruction is e/ecuted in t)e

$o""o*in c#c"e@10 >etc) !n instruction $rom memor#

'0 Decode t)e instruction

70 Re!d t)e e$$ecti(e !ddress $rom memor# i$ t)e instruction )!s !nindirect !ddress

80 E/ecute t)e instruction

A$ter !n instruction is e/ecuted, t)e c#c"e st!rts !!in !tstep 1, $or t)e ne/t instruction

)ote@ E(er# di$$erent processor )!s its o*n +di$$erent.

instruction c#c"e

'1Basic Computer Organization & Design Instruction C

cle

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>ETC !nd DECODE

>etc) !nd Decode T9@ AR PC +S9S1S'

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''Basic Computer Organization & Design


DETERMINE TE TPE O> INSTRUCTION

< 9 +direct.

DKIT7@ AR

MARJDKIKT7@ Not)inDIKT7@ E/ecute ! reister%re$erence instr0

DIT7@ E/ecute !n input%output instr0

Instrction Ccle

St!rtSC

AR

PC

T9

IR

MARJ, PC

PC 1T1

AR

IR+9%11., IIR+14.Decode Opcode in IR+1'%18.,

T'

D

< 9 +Memor#%re$erence.+Reister or I?O. < 1

II

E/ecutereister%re$erence

instructionSC 9

E/ecuteinput%outputinstructionSC 9

MARJAR Not)in

< 9 +reister.+I?O. < 1 +indirect. < 1

T7 T7 T7 T7

E/ecute

memor#%re$erenceinstructionSC 9

T8

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cle

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REGISTER RE>ERENCE INSTRUCTIONS

r < DIT7

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MEMOR RE>ERENCE INSTRUCTIONS

AND to ACD9T8@ DR MARJ Re!d oper!nd

D9T4@ AC AC DR, SC 9 AND *it) AC

ADD to AC

D1T8@ DR MARJ Re!d oper!nd

D1T4@ AC AC DR, E Cout, SC 9 Add to AC !nd store c!rr# in E

% T)e e$$ecti(e !ddress o$ t)e instruction is in AR !nd *!s p"!ced t)ere durintimin sin!" T'*)en I < 9, or durin timin sin!" T7*)en I < 1

% Memor# c#c"e is !ssumed to -e s)ort enou) to comp"ete in ! CPU c#c"e% T)e e/ecution o$ MR instruction st!rts *it) T8

(R Instructions

S#m-o"Oper!tionDecoder

S#m-o"ic Description

AND D9

AC

AC

MARJ

ADD D1 AC AC MARJ, E Cout&DA D' AC MARJ

STA D7 MARJ AC

BUN D8 PC AR

BSA D4 MARJ PC, PC AR 1

ISZ D; MARJ

MARJ 1, i$ MARJ 1 < 9 t)en PC

PC1


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Memor#, PC !$ter e/ecution

'1

9 BSA 174

Ne/t instruction

Su-routine

'9

PC < '1

AR < 174

17;

1 BUN 174

Memor#, PC, AR !t time T8

9 BSA 174

Ne/t instruction

Su-routine

'9

'1

174

PC < 17;

1 BUN 174

Memor# Memor#

&DA@ &o!d to ACD'T8@ DR MARJ

D'T4@ AC

DR, SC

9STA@ Store AC

D7T8@ MARJ AC, SC 9

BUN@ Br!nc) Uncondition!""#D8T8@ PC AR, SC 9

BSA@ Br!nc) !nd S!(e Return Address

MARJ

PC, PC

AR 1

';Basic Computer Organization & Design (R Instructions

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';Basic Computer Organization & Design



(R Instructions

BSA@D4T8@ MARJ PC, AR AR 1

D4T4@ PC AR, SC 9

ISZ@ Increment !nd S2ip%i$%Zero

D;T8@ DR

MARJD;T4@ DR DR 1

D;T8@ MARJ DR, i$ +DR < 9. t)en +PC PC 1., SC 9

'Basic Computer Organization & Design (R Instructions

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p g g


>&O5CART >OR MEMOR RE>ERENCE INSTRUCTIONS

(R Instructions

Memor#%re$erence instruction

DR MARJ DR MARJ DR MARJ MARJ ACSC

9

AND ADD &DA STA

AC

AC DRSC 9

AC

AC DRE

Cout

SC

9

ACDRSC 9

D T9 8 D T1 8 D T' 8 D T7 8

D T9 4 D T1 4 D T' 4

PC

AR

SC

9

MARJ

PC

AR

AR 1

DR

MARJ

BUN BSA ISZ

D T8 8 D T4 8 D T; 8

DR DR 1D T4 4 D T; 4

PC ARSC 9

MARJ DRI$ +DR < 9.t)en +PC PC 1.SC 9

D T; ;

'Basic Computer Organization & Design I.O and Interru

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p g g


INPUT%OUTPUT AND INTERRUPT

Input%Output Con$iur!tion

I)PR Input reister % -itsO*TR Output reister % -its+,I Input $"! % 1 -it+,O Output $"! % 1 -itI-) Interrupt en!-"e % 1 -it

% T)e termin!" sends !nd recei(es seri!" in$orm!tion% T)e seri!" in$o0 $rom t)e 2e#-o!rd is s)i$ted into INPR% T)e seri!" in$o0 $or t)e printer is stored in t)e OUTR% INPR !nd OUTR communic!te *it) t)e termin!"

seri!""# !nd *it) t)e AC in p!r!""e"0% T)e $"!s !re needed to snchronizet)e timin

di$$erence -et*een I?O de(ice !nd t)e computer

A Termin!" *it) ! 2e#-o!rd !nd ! Printer

I.O and Interrupt

Input%outputtermin!"

Seri!"communic!tion

inter$!ce

Computerreisters !nd$"ip%$"ops

Printer

He#-o!rd

Recei(erinter$!ce

Tr!nsmitterinter$!ce

>GOOUTR

AC

INPR >GI

Seri!" Communic!tions P!t)P!r!""e" Communic!tions P!t)

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PROGRAM CONTRO&&ED DATA TRANS>ER

"oop@ I$ >GI < 1 oto "oop

INPR

ne* d!t!, >GI

1

"oop@ I$ >GO < 1 oto "oop

consume OUTR, >GO

1

%% CPU %% %% I?O De(ice %%

? Input ? ? Initi!""# >GI < 9 ? "oop@ I$ >GI < 9 oto "oop

AC

INPR, >GI

9

? Output ? ? Initi!""# >GO < 1 ? "oop@ I$ >GO < 9 oto "oop

OUTR

AC, >GO

9

p

St!rt Input

>GI 9

>GIGO 9

>GOGIGO

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INPUT%OUTPUT INSTRUCTIONS

DIT7< p

IR+i. < Bi, i < ;, , 11

p@ SC

9 C"e!r SCINP pB11@ AC+9%. INPR, >GI 9 Input c)!r0 to AC

OUT pB19@ OUTR AC+9%., >GO 9 Output c)!r0 $rom AC

SHI pB:@ i$+>GI < 1. t)en +PC PC 1. S2ip on input $"!

SHO pB@ i$+>GO < 1. t)en +PC PC 1. S2ip on output $"!

ION pB@ IEN 1 Interrupt en!-"e on

IO> pB;@ IEN 9 Interrupt en!-"e o$$

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PROGRAM%CONTRO&&ED INPUT?OUTPUT

Pror!m%contro""ed I?O% Continuous CPU in(o"(ement

I?O t!2es (!"u!-"e CPU time

% CPU s"o*ed do*n to I?O speed

% Simp"e

% &e!st )!rd*!re

p

Input

&OOP, SHI DE BUN &OOP INP DE

Output

&OOP, &DA DATA &OP, SHO DE BUN &OP OUT DE

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INTERRUPT INITIATED INPUT?OUTPUT

% Open communic!tion on"# *)en some d!t! )!s to -e p!ssed %%L interrupt0

% T)e I?O inter$!ce, inste!d o$ t)e CPU, monitors t)e I?O de(ice0

% 5)en t)e inter$!ce $ounds t)!t t)e I?O de(ice is re!d# $or d!t! tr!ns$er,

it ener!tes !n interrupt re=uest to t)e CPU

% Upon detectin !n interrupt, t)e CPU stops moment!ri"# t)e t!s2

it is doin, -r!nc)es to t)e ser(ice routine to process t)e d!t!tr!ns$er, !nd t)en returns to t)e t!s2 it *!s per$ormin0

IEN +Interrupt%en!-"e $"ip%$"op.

% c!n -e set !nd c"e!red -# instructions% *)en c"e!red, t)e computer c!nnot -e interrupted


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>&O5CART >OR INTERRUPT CC&ER < Interrupt $?$

% T)e interrupt c#c"e is ! 5 imp"ement!tion o$ ! -r!nc)

!nd s!(e return !ddress oper!tion0% At t)e -einnin o$ t)e ne/t instruction c#c"e, t)einstruction t)!t is re!d $rom memor# is in !ddress 10

% At memor# !ddress 1, t)e pror!mmer must store ! -r!nc) instructiont)!t sends t)e contro" to !n interrupt ser(ice routine

% T)e instruction t)!t returns t)e contro" to t)e oriin!"pror!m is indirect BUN 9

Store return !ddress

Retc) !nd decodeinstructions

IEN

>GI

>GO

E/ecuteinstructions

R

1

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REGISTER TRANS>ER OPERATIONS IN INTERRUPT CC&E

Reister Tr!ns$er St!tements $or Interrupt C#c"e% R >?>

1 i$ IEN +>GI >GO.T9T1T'

T9T1T'+IEN.+>GI >GO.@ R 1

% T)e $etc) !nd decode p)!ses o$ t)e instruction c#c"e must -e modi$ied Rep"!ce T9, T1, T' *it) RKT9, RKT1, RKT'% T)e interrupt c#c"e @

RT9@ AR 9, TR PC

RT1@ MARJ TR, PC 9

RT'@ PC

PC 1, IEN

9, R

9, SC

9

A$ter interrupt c#c"e

9 BUN 11'9

9

1

PC < '4;'44

1 BUN 9

Be$ore interrupt

M!inPror!m

11'9

I?OPror!m

9 BUN 11'9

9

PC < 1

'4;'44

1 BUN 9

Memor#

M!inPror!m

11'9

I?OPror!m

'4;


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>URTER QUESTIONS ON INTERRUPT

o* c!n t)e CPU reconi6e t)e de(ice

re=uestin !n interrupt

Since di$$erent de(ices !re "i2e"# to re=uire

di$$erent interrupt ser(ice routines, )o* c!n

t)e CPU o-t!in t)e st!rtin !ddress o$ t)e!ppropri!te routine in e!c) c!se

S)ou"d !n# de(ice -e !""o*ed to interrupt t)e

CPU *)i"e !not)er interrupt is -ein ser(iced

o* c!n t)e situ!tion -e )!nd"ed *)en t*o or

more interrupt re=uests occur simu"t!neous"#

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COMP&ETE COMPUTER DESCRIPTION>"o*c)!rt o$ Oper!tions

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COMP&ETE COMPUTER DESCRIPTIONMicrooper!tions

>etc)

Decode

IndirectInterrupt

Memor#%Re$erence

AND

ADD

&DA

STA BUN

BSA

ISZ

RT9@

RT1@

R

T'@

DIT7@

RT9@

RT1@

RT'@

D9T8@

D9T4@

D1T8@

D1T4@

D'T8@

D'T4@

D7

T8

@

D8T8@

D4T8@

D4T4@

D;T8@

D;T4@

D;T;@

AR PCIR

MARJ, PC

PC 1D9, 000, D

Decode IR+1' 3 18.,AR IR+9 3 11., I IR+14.

AR MARJ

R 1AR

9, TR

PCMARJ

TR, PC

9PC PC 1, IEN 9, R 9, SC 9

DR MARJAC AC DR, SC 9DR

MARJAC

AC DR, E

Cout, SC 9

DR

MARJAC DR, SC 9MARJ

AC, SC

9PC

AR, SC

9

MARJ PC, AR AR 1PC

AR, SC

9DR MARJDR

DR 1MARJ

DR, i$+DR

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Reister%Re$erence

C&A C&E CMA CME CIR CI& INC

SPA SNA SZA SZE &T

Input%Output

INP OUT SHI SHO ION IO>

DIT7< r

IR+i. < Bir@

rB11@

rB19@

rB:@

rB@

rB@

rB;@

rB4@

rB8@

rB7@

rB'@

rB1@

rB9@

DIT7< pIR+i. < Bi

p@ pB11@

pB19@

pB:@

pB@

pB@

pB;@

+Common to !"" reister%re$erence instr.

+i < 9,1,', 000, 11.SC

9AC

9E 9AC

AC

E

E

AC s)r AC, AC+14. E, E AC+9.AC

s)" AC, AC+9.

E, E

AC+14.AC AC 1

I$+AC+14. GIGO

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DESIGN O> BASIC COMPUTER+BC.

!rd*!re Components o$ BC

A memor# unit@ 89:; / 1;0

Reisters@AR, PC, DR, AC, IR, TR, OUTR, INPR, !nd SC>"ip%>"ops+St!tus.@

I, S, E, R, IEN, >GI, !nd >GODecoders@ ! 7/ Opcode decoder ! 8/1; timin decoderCommon -us@ 1; -its

Contro" "oic !tes@Adder !nd &oic circuit@ Connected to AC

Contro" &oic G!tes

% Input Contro"s o$ t)e nine reisters

% Re!d !nd 5rite Contro"s o$ memor#

% Set, C"e!r, or Comp"ement Contro"s o$ t)e $"ip%$"ops

% S', S1, S9 Contro"s to se"ect ! reister $or t)e -us

% AC, !nd Adder !nd &oic circuit


Design of Basic Computer

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CONTRO& O> REGISTERS AND MEMOR

Sc!n !"" o$ t)e reister tr!ns$er st!tements t)!t c)!ne t)e content o$ AR@

&D+AR. < RKT9 RKT' DKIT7C&R+AR. < RT9INR+AR. < D4T8

Address ReisterF AR

RT9@ AR

PC &D+AR.RT'@ AR IR+9%11. &D+AR.

DIT7@ AR MARJ &D+AR.

RT9@ AR 9 C&R+AR.

D4T8@ AR AR 1 INR+AR.

AR

&DINR

C&R

C"oc2

To -us1'

>rom -us1'

DK

I

TT

R

T

D

T

7'

9

8

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CONTRO& O> >&AGS

pB@ IEN 1 +I?O Instruction.

pB;@ IEN

9 +I?O Instruction.RT'@ IEN 9 +Interrupt.

p < DIT7 +Input?Output Instruction.

IEN@ Interrupt En!-"e >"!

D

I

T7

H

Q IENp

B

B;

T'R

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CONTRO& O> COMMON BUS

>or AR D8T8@ PC ARD4T4@ PC AR

/1 < D8T8 D4T4

/1

/'

/7

/8

/4

/;

/

Encoder

S '

S 1

S 9

Mu"tip"e/er

-us se"ect

inputs

/1 /' /7 /8 /4 /; / S' S1 S9se"ectedreister

9 9 9 9 9 9 9 9 9 9 none1 9 9 9 9 9 9 9 9 1 AR9 1 9 9 9 9 9 9 1 9 PC9 9 1 9 9 9 9 9 1 1 DR9 9 9 1 9 9 9 1 9 9 AC9 9 9 9 1 9 9 1 9 1 IR9 9 9 9 9 1 9 1 1 9 TR9 9 9 9 9 9 1 1 1 1 Memor#


gn of AC Logic

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DESIGN O> ACCUMU&ATOR &OGIC

Circuits !ssoci!ted *it) AC

A"" t)e st!tements t)!t c)!ne t)e content o$ AC

1;

1;

Adder !nd

"oiccircuit

1;

AC>rom DR

>rom INPR

Contro"

!tes

&D INR C&R

1;

To -us

C"oc2

D9T4@ AC AC DR AND *it) DR

D1T4@ AC AC DR Add *it) DR

D'T4@ AC DR Tr!ns$er $rom DRpB11@ AC+9%. INPR Tr!ns$er $rom INPR

rB:@ AC AC Comp"ement

rB@ AC s)r AC, AC+14. E S)i$t ri)t

rB;@ AC s)" AC, AC+9. E S)i$t "e$t

rB11@ AC 9 C"e!r

rB4@ AC AC 1 Increment


Design of AC Logic

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CONTRO& O> AC REGISTER

G!te structures $or contro""in

t)e &D, INR, !nd C&R o$ AC

AC

&D

INR

C&R

C"oc2

To -us1;>rom Adder

!nd &oic1;

AND

ADD

DR

INPR

COM

SR

S&

INC

C&R

D9

D1

D'

B11

B:

B

B;

B4

B11

r

p

T4

T4


gn of AC Logic

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A&U +ADDER AND &OGIC CIRCUIT.

One st!e o$ Adder !nd &oic circuit

AND

ADD

DR

INPR

COM

SR

S&

H

QAC+i.

&D

>A

C

C

>romINPR-it+i.

DR+i.AC+i.

AC+i1.

AC+i%1.

i

i

i1

I

Unit3_ Ch1 COA

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Transcript of Unit3_ Ch1 COA